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Commit d887a1ce authored by Michael Hennerich's avatar Michael Hennerich Committed by Mike Frysinger
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Blackfin: cpufreq: use a constant latency 



PLL_LOCKCNT applies only to the PLL programming sequence which does not
apply to core and system clock dividers.  Writes to PLL_DIV to change the
CSEL/SSEL dividers take effect immediately.

There is still overhead in software in writing the new dividers, so just
use a value of 50us as this should be good enough.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 21b03cfe

arch/blackfin/mach-common/cpufreq.c

+2 −1
Original line number Diff line number Diff line
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) 
						 dpm_state_table[index].tscale);

	}



	policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;

	policy->cpuinfo.transition_latency = 50000; /* 50us assumed */



	/*Now ,only support one cpu */

	policy->cur = cclk;

	cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);