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Commit d87ce764 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Jani Nikula
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drm/i915: Add .get_hw_state() method for planes 

Add a .get_hw_state() method for planes, returning true or false
depending on whether the plane is enabled. Use it to rewrite the
plane enabled/disabled asserts in platform agnostic fashion.

We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
supposed sanitize that anyway it doesn't really matter.

v2: Reoder patches to not depend on enum old_plane_id
    Just call assert_plane_disabled() from assert_planes_disabled()
v3: Deal with disabled power wells in .get_hw_state()
v4: Rebase due skl primary plane code removal

Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> #v2
Tested-by: Thierry Reding <thierry.reding@gmail.com> #v2
Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-2-ville.syrjala@linux.intel.com


Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
(cherry picked from commit 51f5a096)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent a8750ddc

drivers/gpu/drm/i915/intel_display.c

+90 −98
Original line number Diff line number Diff line
@@ -1211,23 +1211,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) 
	     pipe_name(pipe));

}



static void assert_cursor(struct drm_i915_private *dev_priv,

			  enum pipe pipe, bool state)

{

	bool cur_state;



	if (IS_I845G(dev_priv) || IS_I865G(dev_priv))

		cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;

	else

		cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;



	I915_STATE_WARN(cur_state != state,

	     "cursor on pipe %c assertion failure (expected %s, current %s)\n",

			pipe_name(pipe), onoff(state), onoff(cur_state));

}

#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)

#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)



void assert_pipe(struct drm_i915_private *dev_priv,

		 enum pipe pipe, bool state)

{
@@ -1255,77 +1238,25 @@ void assert_pipe(struct drm_i915_private *dev_priv, 
			pipe_name(pipe), onoff(state), onoff(cur_state));

}



static void assert_plane(struct drm_i915_private *dev_priv,

			 enum plane plane, bool state)

static void assert_plane(struct intel_plane *plane, bool state)

{

	u32 val;

	bool cur_state;

	bool cur_state = plane->get_hw_state(plane);



	val = I915_READ(DSPCNTR(plane));

	cur_state = !!(val & DISPLAY_PLANE_ENABLE);

	I915_STATE_WARN(cur_state != state,

	     "plane %c assertion failure (expected %s, current %s)\n",

			plane_name(plane), onoff(state), onoff(cur_state));

			"%s assertion failure (expected %s, current %s)\n",

			plane->base.name, onoff(state), onoff(cur_state));

}



#define assert_plane_enabled(d, p) assert_plane(d, p, true)

#define assert_plane_disabled(d, p) assert_plane(d, p, false)

#define assert_plane_enabled(p) assert_plane(p, true)

#define assert_plane_disabled(p) assert_plane(p, false)



static void assert_planes_disabled(struct drm_i915_private *dev_priv,

				   enum pipe pipe)

static void assert_planes_disabled(struct intel_crtc *crtc)

{

	int i;



	/* Primary planes are fixed to pipes on gen4+ */

	if (INTEL_GEN(dev_priv) >= 4) {

		u32 val = I915_READ(DSPCNTR(pipe));

		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,

		     "plane %c assertion failure, should be disabled but not\n",

		     plane_name(pipe));

		return;

	}



	/* Need to check both planes against the pipe */

	for_each_pipe(dev_priv, i) {

		u32 val = I915_READ(DSPCNTR(i));

		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>

			DISPPLANE_SEL_PIPE_SHIFT;

		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,

		     "plane %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(i), pipe_name(pipe));

	}

}



static void assert_sprites_disabled(struct drm_i915_private *dev_priv,

				    enum pipe pipe)

{

	int sprite;

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_plane *plane;



	if (INTEL_GEN(dev_priv) >= 9) {

		for_each_sprite(dev_priv, pipe, sprite) {

			u32 val = I915_READ(PLANE_CTL(pipe, sprite));

			I915_STATE_WARN(val & PLANE_CTL_ENABLE,

			     "plane %d assertion failure, should be off on pipe %c but is still active\n",

			     sprite, pipe_name(pipe));

		}

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		for_each_sprite(dev_priv, pipe, sprite) {

			u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));

			I915_STATE_WARN(val & SP_ENABLE,

			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

			     sprite_name(pipe, sprite), pipe_name(pipe));

		}

	} else if (INTEL_GEN(dev_priv) >= 7) {

		u32 val = I915_READ(SPRCTL(pipe));

		I915_STATE_WARN(val & SPRITE_ENABLE,

		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(pipe), pipe_name(pipe));

	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {

		u32 val = I915_READ(DVSCNTR(pipe));

		I915_STATE_WARN(val & DVS_ENABLE,

		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",

		     plane_name(pipe), pipe_name(pipe));

	}

	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)

		assert_plane_disabled(plane);

}



static void assert_vblank_disabled(struct drm_crtc *crtc)
@@ -1918,9 +1849,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) 


	DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));



	assert_planes_disabled(dev_priv, pipe);

	assert_cursor_disabled(dev_priv, pipe);

	assert_sprites_disabled(dev_priv, pipe);

	assert_planes_disabled(crtc);



	/*

	 * A pipe without a PLL won't actually be able to drive bits from
@@ -1989,9 +1918,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc) 
	 * Make sure planes won't keep trying to pump pixels to us,

	 * or we might hang the display.

	 */

	assert_planes_disabled(dev_priv, pipe);

	assert_cursor_disabled(dev_priv, pipe);

	assert_sprites_disabled(dev_priv, pipe);

	assert_planes_disabled(crtc);



	reg = PIPECONF(cpu_transcoder);

	val = I915_READ(reg);
@@ -3385,6 +3312,31 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary, 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool i9xx_plane_get_hw_state(struct intel_plane *primary)

{



	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane plane = primary->plane;

	enum pipe pipe = primary->pipe;

	bool ret;



	/*

	 * Not 100% correct for planes that can move between pipes,

	 * but that's only the case for gen2-4 which don't have any

	 * display power wells.

	 */

	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32

intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)

{
@@ -4866,7 +4818,8 @@ void hsw_enable_ips(struct intel_crtc *crtc) 
	 * a vblank wait.

	 */



	assert_plane_enabled(dev_priv, crtc->plane);

	assert_plane_enabled(to_intel_plane(crtc->base.primary));



	if (IS_BROADWELL(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
@@ -4899,7 +4852,8 @@ void hsw_disable_ips(struct intel_crtc *crtc) 
	if (!crtc->config->ips_enabled)

		return;



	assert_plane_enabled(dev_priv, crtc->plane);

	assert_plane_enabled(to_intel_plane(crtc->base.primary));



	if (IS_BROADWELL(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
@@ -9477,6 +9431,23 @@ static void i845_disable_cursor(struct intel_plane *plane, 
	i845_update_cursor(plane, NULL, NULL);

}



static bool i845_cursor_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(PIPE_A);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,

			   const struct intel_plane_state *plane_state)

{
@@ -9670,6 +9641,28 @@ static void i9xx_disable_cursor(struct intel_plane *plane, 
	i9xx_update_cursor(plane, NULL, NULL);

}



static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	/*

	 * Not 100% correct for planes that can move between pipes,

	 * but that's only the case for gen2-3 which don't have any

	 * display power wells.

	 */

	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



/* VESA 640x480x72Hz mode to set on the pipe */

static const struct drm_display_mode load_detect_mode = {
@@ -13205,6 +13198,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = skl_update_plane;

		primary->disable_plane = skl_disable_plane;

		primary->get_hw_state = skl_plane_get_hw_state;

	} else if (INTEL_GEN(dev_priv) >= 9) {

		intel_primary_formats = skl_primary_formats;

		num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13215,6 +13209,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = skl_update_plane;

		primary->disable_plane = skl_disable_plane;

		primary->get_hw_state = skl_plane_get_hw_state;

	} else if (INTEL_GEN(dev_priv) >= 4) {

		intel_primary_formats = i965_primary_formats;

		num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -13222,6 +13217,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = i9xx_update_primary_plane;

		primary->disable_plane = i9xx_disable_primary_plane;

		primary->get_hw_state = i9xx_plane_get_hw_state;

	} else {

		intel_primary_formats = i8xx_primary_formats;

		num_formats = ARRAY_SIZE(i8xx_primary_formats);
@@ -13229,6 +13225,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 


		primary->update_plane = i9xx_update_primary_plane;

		primary->disable_plane = i9xx_disable_primary_plane;

		primary->get_hw_state = i9xx_plane_get_hw_state;

	}



	if (INTEL_GEN(dev_priv) >= 9)
@@ -13318,10 +13315,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, 
	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {

		cursor->update_plane = i845_update_cursor;

		cursor->disable_plane = i845_disable_cursor;

		cursor->get_hw_state = i845_cursor_get_hw_state;

		cursor->check_plane = i845_check_cursor;

	} else {

		cursor->update_plane = i9xx_update_cursor;

		cursor->disable_plane = i9xx_disable_cursor;

		cursor->get_hw_state = i9xx_cursor_get_hw_state;

		cursor->check_plane = i9xx_check_cursor;

	}
@@ -14671,8 +14670,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
	DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",

		      pipe_name(pipe));



	assert_plane_disabled(dev_priv, PLANE_A);

	assert_plane_disabled(dev_priv, PLANE_B);

	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));

	assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));



	I915_WRITE(PIPECONF(pipe), 0);

	POSTING_READ(PIPECONF(pipe));
@@ -14885,20 +14884,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv) 
	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

}



static bool primary_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);



	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;

}



/* FIXME read out full plane state for all planes */

static void readout_plane_state(struct intel_crtc *crtc)

{

	struct intel_plane *primary = to_intel_plane(crtc->base.primary);

	bool visible;



	visible = crtc->active && primary_get_hw_state(primary);

	visible = crtc->active && primary->get_hw_state(primary);



	intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),

				to_intel_plane_state(primary->base.state),

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -862,6 +862,7 @@ struct intel_plane { 
			     const struct intel_plane_state *plane_state);

	void (*disable_plane)(struct intel_plane *plane,

			      struct intel_crtc *crtc);

	bool (*get_hw_state)(struct intel_plane *plane);

	int (*check_plane)(struct intel_plane *plane,

			   struct intel_crtc_state *crtc_state,

			   struct intel_plane_state *state);
@@ -1924,6 +1925,7 @@ void skl_update_plane(struct intel_plane *plane, 
		      const struct intel_crtc_state *crtc_state,

		      const struct intel_plane_state *plane_state);

void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);

bool skl_plane_get_hw_state(struct intel_plane *plane);



/* intel_tv.c */

void intel_tv_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_sprite.c

+83 −0
Original line number Diff line number Diff line
@@ -329,6 +329,26 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



bool

skl_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static void

chv_update_csc(struct intel_plane *plane, uint32_t format)

{
@@ -506,6 +526,26 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

vlv_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,

			  const struct intel_plane_state *plane_state)

{
@@ -646,6 +686,25 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

ivb_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,

			  const struct intel_plane_state *plane_state)

{
@@ -777,6 +836,25 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool

g4x_plane_get_hw_state(struct intel_plane *plane)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum intel_display_power_domain power_domain;

	enum pipe pipe = plane->pipe;

	bool ret;



	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))

		return false;



	ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;



	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



static int

intel_check_sprite_plane(struct intel_plane *plane,

			 struct intel_crtc_state *crtc_state,
@@ -1232,6 +1310,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = skl_update_plane;

		intel_plane->disable_plane = skl_disable_plane;

		intel_plane->get_hw_state = skl_plane_get_hw_state;



		plane_formats = skl_plane_formats;

		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1242,6 +1321,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = skl_update_plane;

		intel_plane->disable_plane = skl_disable_plane;

		intel_plane->get_hw_state = skl_plane_get_hw_state;



		plane_formats = skl_plane_formats;

		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
@@ -1252,6 +1332,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = vlv_update_plane;

		intel_plane->disable_plane = vlv_disable_plane;

		intel_plane->get_hw_state = vlv_plane_get_hw_state;



		plane_formats = vlv_plane_formats;

		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
@@ -1267,6 +1348,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = ivb_update_plane;

		intel_plane->disable_plane = ivb_disable_plane;

		intel_plane->get_hw_state = ivb_plane_get_hw_state;



		plane_formats = snb_plane_formats;

		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1277,6 +1359,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, 


		intel_plane->update_plane = g4x_update_plane;

		intel_plane->disable_plane = g4x_disable_plane;

		intel_plane->get_hw_state = g4x_plane_get_hw_state;



		modifiers = i9xx_plane_format_modifiers;

		if (IS_GEN6(dev_priv)) {