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Unverified Commit d843dd53 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by James Hogan
Browse files

MIPS: mscc: Add ocelot dtsi 



Add a device tree include file for the Microsemi Ocelot SoC.

Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Allan Nielsen <Allan.Nielsen@microsemi.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/18855/


Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
parent 2707177e

arch/mips/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon 
subdir-y	+= img

subdir-y	+= ingenic

subdir-y	+= lantiq

subdir-y	+= mscc

subdir-y	+= mti

subdir-y	+= netlogic

subdir-y	+= ni

arch/mips/boot/dts/mscc/Makefile

0 → 100644
+1 −0
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obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))

arch/mips/boot/dts/mscc/ocelot.dtsi

0 → 100644
+117 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2017 Microsemi Corporation */



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "mscc,ocelot";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "mips,mips24KEc";

			device_type = "cpu";

			clocks = <&cpu_clk>;

			reg = <0>;

		};

	};



	aliases {

		serial0 = &uart0;

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

		interrupt-controller;

		compatible = "mti,cpu-interrupt-controller";

	};



	cpu_clk: cpu-clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <500000000>;

	};



	ahb_clk: ahb-clk {

		compatible = "fixed-factor-clock";

		#clock-cells = <0>;

		clocks = <&cpu_clk>;

		clock-div = <2>;

		clock-mult = <1>;

	};



	ahb@70000000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x70000000 0x2000000>;



		interrupt-parent = <&intc>;



		cpu_ctrl: syscon@0 {

			compatible = "mscc,ocelot-cpu-syscon", "syscon";

			reg = <0x0 0x2c>;

		};



		intc: interrupt-controller@70 {

			compatible = "mscc,ocelot-icpu-intr";

			reg = <0x70 0x70>;

			#interrupt-cells = <1>;

			interrupt-controller;

			interrupt-parent = <&cpuintc>;

			interrupts = <2>;

		};



		uart0: serial@100000 {

			pinctrl-0 = <&uart_pins>;

			pinctrl-names = "default";

			compatible = "ns16550a";

			reg = <0x100000 0x20>;

			interrupts = <6>;

			clocks = <&ahb_clk>;

			reg-io-width = <4>;

			reg-shift = <2>;



			status = "disabled";

		};



		uart2: serial@100800 {

			pinctrl-0 = <&uart2_pins>;

			pinctrl-names = "default";

			compatible = "ns16550a";

			reg = <0x100800 0x20>;

			interrupts = <7>;

			clocks = <&ahb_clk>;

			reg-io-width = <4>;

			reg-shift = <2>;



			status = "disabled";

		};



		reset@1070008 {

			compatible = "mscc,ocelot-chip-reset";

			reg = <0x1070008 0x4>;

		};



		gpio: pinctrl@1070034 {

			compatible = "mscc,ocelot-pinctrl";

			reg = <0x1070034 0x68>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&gpio 0 0 22>;



			uart_pins: uart-pins {

				pins = "GPIO_6", "GPIO_7";

				function = "uart";

			};



			uart2_pins: uart2-pins {

				pins = "GPIO_12", "GPIO_13";

				function = "uart2";

			};

		};

	};

};