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Commit d8197317 authored by Kai Chen's avatar Kai Chen Committed by Jani Nikula
Browse files

drm/i915: Remove decoupled MMIO code 



This is a follow-up patch to the previous patch ([PATCH[1/2] drm/i915:
Disable decoupled MMIO) to remove the dead code for decoupled MMIO
implementation, as it won't be used any longer on GEN9LP.

Therefore, this patch reverts:

commit 85ee17eb
Author: Praveen Paneri <praveen.paneri@intel.com>
Date:   Tue Nov 15 22:49:20 2016 +0530

    drm/i915/bxt: Broxton decoupled MMIO

Signed-off-by: default avatarKai Chen <kai.chen@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170523215812.18328-3-kai.chen@intel.com
parent 0051c10a

drivers/gpu/drm/i915/i915_drv.h

+0 −3
Original line number Diff line number Diff line
@@ -751,7 +751,6 @@ struct intel_csr { 
	func(has_aliasing_ppgtt); \

	func(has_csr); \

	func(has_ddi); \

	func(has_decoupled_mmio); \

	func(has_dp_mst); \

	func(has_fbc); \

	func(has_fpga_dbg); \
@@ -2995,8 +2994,6 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define GT_FREQUENCY_MULTIPLIER 50

#define GEN9_FREQ_SCALER 3



#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)



#include "i915_trace.h"



static inline bool intel_vtd_active(void)

drivers/gpu/drm/i915/i915_reg.h

+0 −7
Original line number Diff line number Diff line
@@ -7792,13 +7792,6 @@ enum { 
#define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)

#define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)



/* Decoupled MMIO register pair for kernel driver */

#define GEN9_DECOUPLED_REG0_DW0			_MMIO(0xF00)

#define GEN9_DECOUPLED_REG0_DW1			_MMIO(0xF04)

#define GEN9_DECOUPLED_DW1_GO			(1<<31)

#define GEN9_DECOUPLED_PD_SHIFT			28

#define GEN9_DECOUPLED_OP_SHIFT			24



/* Per-pipe DDI Function Control */

#define _TRANS_DDI_FUNC_CTL_A		0x60400

#define _TRANS_DDI_FUNC_CTL_B		0x61400

drivers/gpu/drm/i915/intel_uncore.c

+0 −126
Original line number Diff line number Diff line
@@ -404,8 +404,6 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 
static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,

					  bool restore_forcewake)

{

	struct intel_device_info *info = mkwrite_device_info(dev_priv);



	/* clear out unclaimed reg detection bit */

	if (check_for_unclaimed_mmio(dev_priv))

		DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
@@ -418,9 +416,6 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, 
				   GT_FIFO_CTL_RC6_POLICY_STALL);

	}



	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))

		info->has_decoupled_mmio = false;



	intel_uncore_forcewake_reset(dev_priv, restore_forcewake);

}
@@ -810,78 +805,6 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv, 
	__unclaimed_reg_debug(dev_priv, reg, read, before);

}



enum decoupled_power_domain {

	GEN9_DECOUPLED_PD_BLITTER = 0,

	GEN9_DECOUPLED_PD_RENDER,

	GEN9_DECOUPLED_PD_MEDIA,

	GEN9_DECOUPLED_PD_ALL

};



enum decoupled_ops {

	GEN9_DECOUPLED_OP_WRITE = 0,

	GEN9_DECOUPLED_OP_READ

};



static const enum decoupled_power_domain fw2dpd_domain[] = {

	GEN9_DECOUPLED_PD_RENDER,

	GEN9_DECOUPLED_PD_BLITTER,

	GEN9_DECOUPLED_PD_ALL,

	GEN9_DECOUPLED_PD_MEDIA,

	GEN9_DECOUPLED_PD_ALL,

	GEN9_DECOUPLED_PD_ALL,

	GEN9_DECOUPLED_PD_ALL

};



/*

 * Decoupled MMIO access for only 1 DWORD

 */

static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,

					 u32 reg,

					 enum forcewake_domains fw_domain,

					 enum decoupled_ops operation)

{

	enum decoupled_power_domain dp_domain;

	u32 ctrl_reg_data = 0;



	dp_domain = fw2dpd_domain[fw_domain - 1];



	ctrl_reg_data |= reg;

	ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);

	ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);

	ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;

	__raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);



	if (wait_for_atomic((__raw_i915_read32(dev_priv,

			    GEN9_DECOUPLED_REG0_DW1) &

			    GEN9_DECOUPLED_DW1_GO) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Decoupled MMIO wait timed out\n");

}



static inline u32

__gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,

			     u32 reg,

			     enum forcewake_domains fw_domain)

{

	__gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,

				     GEN9_DECOUPLED_OP_READ);



	return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);

}



static inline void

__gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,

			    u32 reg, u32 data,

			    enum forcewake_domains fw_domain)

{



	__raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);



	__gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,

				     GEN9_DECOUPLED_OP_WRITE);

}





#define GEN2_READ_HEADER(x) \

	u##x val = 0; \

	assert_rpm_wakelock_held(dev_priv);
@@ -978,28 +901,6 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { 
#define __gen6_read(x) __gen_read(gen6, x)

#define __fwtable_read(x) __gen_read(fwtable, x)



#define __gen9_decoupled_read(x) \

static u##x \

gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \

		       i915_reg_t reg, bool trace) { \

	enum forcewake_domains fw_engine; \

	GEN6_READ_HEADER(x); \

	fw_engine = __fwtable_reg_read_fw_domains(offset); \

	if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \

		unsigned i; \

		u32 *ptr_data = (u32 *) &val; \

		for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \

			*ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \

								 offset, \

								 fw_engine); \

	} else { \

		val = __raw_i915_read##x(dev_priv, reg); \

	} \

	GEN6_READ_FOOTER; \

}



__gen9_decoupled_read(32)

__gen9_decoupled_read(64)

__fwtable_read(8)

__fwtable_read(16)

__fwtable_read(32)
@@ -1086,25 +987,6 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo 
#define __gen8_write(x) __gen_write(gen8, x)

#define __fwtable_write(x) __gen_write(fwtable, x)



#define __gen9_decoupled_write(x) \

static void \

gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \

			i915_reg_t reg, u##x val, \

		bool trace) { \

	enum forcewake_domains fw_engine; \

	GEN6_WRITE_HEADER; \

	fw_engine = __fwtable_reg_write_fw_domains(offset); \

	if (fw_engine & ~dev_priv->uncore.fw_domains_active) \

		__gen9_decoupled_mmio_write(dev_priv, \

					    offset, \

					    val, \

					    fw_engine); \

	else \

		__raw_i915_write##x(dev_priv, reg, val); \

	GEN6_WRITE_FOOTER; \

}



__gen9_decoupled_write(32)

__fwtable_write(8)

__fwtable_write(16)

__fwtable_write(32)
@@ -1341,14 +1223,6 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) 
		ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);

		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);

		ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);

		if (HAS_DECOUPLED_MMIO(dev_priv)) {

			dev_priv->uncore.funcs.mmio_readl =

						gen9_decoupled_read32;

			dev_priv->uncore.funcs.mmio_readq =

						gen9_decoupled_read64;

			dev_priv->uncore.funcs.mmio_writel =

						gen9_decoupled_write32;

		}

	}



	iosf_mbi_register_pmic_bus_access_notifier(