Commit d7f3ec2b authored Jul 09, 2014 by Gregory CLEMENT Committed by Jason Cooper Jul 16, 2014

ARM: mvebu: add CA9 MPcore SoC Controller node



The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.

Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com


Signed-off-by: Jason Cooper <jason@lakedaemon.net>

parent 9495898f

Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt

0 → 100644

+14 −0

Original line number	Diff line number	Diff line
		Marvell Armada 38x CA9 MPcore SoC Controller
		============================================

		Required properties:

		- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".

		- reg: should be the register base and length as documented in the
		datasheet for the CA9 MPcore SoC Control registers

		mpcore-soc-ctrl@20d20 {
		compatible = "marvell,armada-380-mpcore-soc-ctrl";
		reg = <0x20d20 0x6c>;
		};

arch/arm/boot/dts/armada-38x.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -286,6 +286,11 @@
		reg = <0x20800 0x10>;
		};

		mpcore-soc-ctrl@20d20 {
		compatible = "marvell,armada-380-mpcore-soc-ctrl";
		reg = <0x20d20 0x6c>;
		};

		coherency-fabric@21010 {
		compatible = "marvell,armada-380-coherency-fabric";
		reg = <0x21010 0x1c>;