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Commit d7c9ade2 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Cyrille Pitchen
Browse files

mtd: spi-nor: add Dual and Quad read mode support to some flash devices 



These devices are used on OpenPOWER systems. The SPI_NOR_DUAL_READ
flags is added for the Aspeed SoCs which do not support QUAD reads.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
parent ce398a81

drivers/mtd/spi-nor/spi-nor.c

+4 −4
Original line number Diff line number Diff line
@@ -1008,10 +1008,10 @@ static const struct flash_info spi_nor_ids[] = { 
	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },

	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },

	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },

	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },

	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },

	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },

	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },

	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
@@ -1023,7 +1023,7 @@ static const struct flash_info spi_nor_ids[] = { 
	{ "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
@@ -1146,7 +1146,7 @@ static const struct flash_info spi_nor_ids[] = { 
	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },

	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },

	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },

	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },

	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,

			SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },