davinci: edma: use BIT() wherever possible (d78a9494) · Commits · e / devices / android_kernel_teracube_emerald

arch/arm/mach-davinci/dma.c

+21 −21

Original line number	Original line	Diff line number	Diff line
	@@ -312,16 +312,16 @@ setup_dma_interrupt(unsigned lch,

	if (!callback)		if (!callback)
	edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
	(1 << (lch & 0x1f)));		BIT(lch & 0x1f));

	edma_cc[ctlr]->intr_data[lch].callback = callback;		edma_cc[ctlr]->intr_data[lch].callback = callback;
	edma_cc[ctlr]->intr_data[lch].data = data;		edma_cc[ctlr]->intr_data[lch].data = data;

	if (callback) {		if (callback) {
	edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
	(1 << (lch & 0x1f)));		BIT(lch & 0x1f));
	edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
	(1 << (lch & 0x1f)));		BIT(lch & 0x1f));
	}		}
	}		}

	@@ -374,7 +374,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
	SH_IER, j) & BIT(i))) {		SH_IER, j) & BIT(i))) {
	/* Clear the corresponding IPR bits */		/* Clear the corresponding IPR bits */
	edma_shadow0_write_array(ctlr, SH_ICR, j,		edma_shadow0_write_array(ctlr, SH_ICR, j,
	(1 << i));		BIT(i));
	if (edma_cc[ctlr]->intr_data[k].callback)		if (edma_cc[ctlr]->intr_data[k].callback)
	edma_cc[ctlr]->intr_data[k].callback(		edma_cc[ctlr]->intr_data[k].callback(
	k, DMA_COMPLETE,		k, DMA_COMPLETE,
	@@ -423,13 +423,13 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
	for (i = 0; i < 32; i++) {		for (i = 0; i < 32; i++) {
	int k = (j << 5) + i;		int k = (j << 5) + i;
	if (edma_read_array(ctlr, EDMA_EMR, j) &		if (edma_read_array(ctlr, EDMA_EMR, j) &
	(1 << i)) {		BIT(i)) {
	/* Clear the corresponding EMR bits */		/* Clear the corresponding EMR bits */
	edma_write_array(ctlr, EDMA_EMCR, j,		edma_write_array(ctlr, EDMA_EMCR, j,
	1 << i);		BIT(i));
	/* Clear any SER */		/* Clear any SER */
	edma_shadow0_write_array(ctlr, SH_SECR,		edma_shadow0_write_array(ctlr, SH_SECR,
	j, (1 << i));		j, BIT(i));
	if (edma_cc[ctlr]->intr_data[k].		if (edma_cc[ctlr]->intr_data[k].
	callback) {		callback) {
	edma_cc[ctlr]->intr_data[k].		edma_cc[ctlr]->intr_data[k].
	@@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
	dev_dbg(data, "QEMR %02x\n",		dev_dbg(data, "QEMR %02x\n",
	edma_read(ctlr, EDMA_QEMR));		edma_read(ctlr, EDMA_QEMR));
	for (i = 0; i < 8; i++) {		for (i = 0; i < 8; i++) {
	if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {		if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
	/* Clear the corresponding IPR bits */		/* Clear the corresponding IPR bits */
	edma_write(ctlr, EDMA_QEMCR, 1 << i);		edma_write(ctlr, EDMA_QEMCR, BIT(i));
	edma_shadow0_write(ctlr, SH_QSECR,		edma_shadow0_write(ctlr, SH_QSECR,
	(1 << i));		BIT(i));

	/* NOTE: not reported!! */		/* NOTE: not reported!! */
	}		}
	@@ -460,9 +460,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
	* to just write CCERRCLR with CCERR value...		* to just write CCERRCLR with CCERR value...
	*/		*/
	for (i = 0; i < 8; i++) {		for (i = 0; i < 8; i++) {
	if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {		if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
	/* Clear the corresponding IPR bits */		/* Clear the corresponding IPR bits */
	edma_write(ctlr, EDMA_CCERRCLR, 1 << i);		edma_write(ctlr, EDMA_CCERRCLR, BIT(i));

	/* NOTE: not reported!! */		/* NOTE: not reported!! */
	}		}
	@@ -666,7 +666,7 @@ int edma_alloc_channel(int channel,
	}		}

	/* ensure access through shadow region 0 */		/* ensure access through shadow region 0 */
	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));		edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));

	/* ensure no events are pending */		/* ensure no events are pending */
	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));		edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
	@@ -1204,7 +1204,7 @@ void edma_pause(unsigned channel)
	channel = EDMA_CHAN_SLOT(channel);		channel = EDMA_CHAN_SLOT(channel);

	if (channel < edma_cc[ctlr]->num_channels) {		if (channel < edma_cc[ctlr]->num_channels) {
	unsigned int mask = (1 << (channel & 0x1f));		unsigned int mask = BIT(channel & 0x1f);

	edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
	}		}
	@@ -1225,7 +1225,7 @@ void edma_resume(unsigned channel)
	channel = EDMA_CHAN_SLOT(channel);		channel = EDMA_CHAN_SLOT(channel);

	if (channel < edma_cc[ctlr]->num_channels) {		if (channel < edma_cc[ctlr]->num_channels) {
	unsigned int mask = (1 << (channel & 0x1f));		unsigned int mask = BIT(channel & 0x1f);

	edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
	}		}
	@@ -1252,7 +1252,7 @@ int edma_start(unsigned channel)

	if (channel < edma_cc[ctlr]->num_channels) {		if (channel < edma_cc[ctlr]->num_channels) {
	int j = channel >> 5;		int j = channel >> 5;
	unsigned int mask = (1 << (channel & 0x1f));		unsigned int mask = BIT(channel & 0x1f);

	/* EDMA channels without event association */		/* EDMA channels without event association */
	if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
	@@ -1298,7 +1298,7 @@ void edma_stop(unsigned channel)

	if (channel < edma_cc[ctlr]->num_channels) {		if (channel < edma_cc[ctlr]->num_channels) {
	int j = channel >> 5;		int j = channel >> 5;
	unsigned int mask = (1 << (channel & 0x1f));		unsigned int mask = BIT(channel & 0x1f);

	edma_shadow0_write_array(ctlr, SH_EECR, j, mask);		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
	edma_shadow0_write_array(ctlr, SH_ECR, j, mask);		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
	@@ -1337,7 +1337,7 @@ void edma_clean_channel(unsigned channel)

	if (channel < edma_cc[ctlr]->num_channels) {		if (channel < edma_cc[ctlr]->num_channels) {
	int j = (channel >> 5);		int j = (channel >> 5);
	unsigned int mask = 1 << (channel & 0x1f);		unsigned int mask = BIT(channel & 0x1f);

	pr_debug("EDMA: EMR%d %08x\n", j,		pr_debug("EDMA: EMR%d %08x\n", j,
	edma_read_array(ctlr, EDMA_EMR, j));		edma_read_array(ctlr, EDMA_EMR, j));
	@@ -1346,7 +1346,7 @@ void edma_clean_channel(unsigned channel)
	edma_write_array(ctlr, EDMA_EMCR, j, mask);		edma_write_array(ctlr, EDMA_EMCR, j, mask);
	/* Clear any SER */		/* Clear any SER */
	edma_shadow0_write_array(ctlr, SH_SECR, j, mask);		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
	edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) \| 0x3);		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) \| BIT(1) \| BIT(0));
	}		}
	}		}
	EXPORT_SYMBOL(edma_clean_channel);		EXPORT_SYMBOL(edma_clean_channel);
	@@ -1366,9 +1366,9 @@ void edma_clear_event(unsigned channel)
	if (channel >= edma_cc[ctlr]->num_channels)		if (channel >= edma_cc[ctlr]->num_channels)
	return;		return;
	if (channel < 32)		if (channel < 32)
	edma_write(ctlr, EDMA_ECR, 1 << channel);		edma_write(ctlr, EDMA_ECR, BIT(channel));
	else		else
	edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
	}		}
	EXPORT_SYMBOL(edma_clear_event);		EXPORT_SYMBOL(edma_clear_event);