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Commit d704b2d3 authored by Aaron Brice's avatar Aaron Brice Committed by Greg Kroah-Hartman
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tty: serial: fsl_lpuart: Fix Tx DMA edge case 



In the case where head == 0 on the circular buffer, there should be one
DMA buffer, not two.  The second zero-length buffer would break the
lpuart driver, transfer would never complete.

Signed-off-by: default avatarAaron Brice <aaron.brice@datasoft.com>
Acked-by: default avatarStefan Agner <stefan@agner.ch>
Tested-by: default avatarStefan Agner <stefan@agner.ch>
Tested-by: default avatarBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f00a7c57

drivers/tty/serial/fsl_lpuart.c

+1 −2
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ static void lpuart_dma_tx(struct lpuart_port *sport) 


	sport->dma_tx_bytes = uart_circ_chars_pending(xmit);



	if (xmit->tail < xmit->head) {

	if (xmit->tail < xmit->head || xmit->head == 0) {

		sport->dma_tx_nents = 1;

		sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);

	} else {
@@ -359,7 +359,6 @@ static void lpuart_dma_tx(struct lpuart_port *sport) 
	sport->dma_tx_in_progress = true;

	sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);

	dma_async_issue_pending(sport->dma_tx_chan);



}



static void lpuart_dma_tx_complete(void *arg)