powerpc/85xx: Add support for SMP initialization (d5b26db2) · Commits · e / devices / android_kernel_teracube_emerald

arch/powerpc/kernel/head_fsl_booke.S

+70 −0

Original line number	Original line	Diff line number	Diff line
	@@ -92,6 +92,7 @@ _ENTRY(_start);
	* if needed		* if needed
	*/		*/

			_ENTRY(__early_start)
	/* 1. Find the index of the entry we're executing in */		/* 1. Find the index of the entry we're executing in */
	bl invstr /* Find our address */		bl invstr /* Find our address */
	invstr: mflr r6 /* Make it accessible */		invstr: mflr r6 /* Make it accessible */
	@@ -348,6 +349,15 @@ skpinv: addi r6,r6,1 /* Increment */
	mtspr SPRN_DBSR,r2		mtspr SPRN_DBSR,r2
	#endif		#endif

			#ifdef CONFIG_SMP
			/* Check to see if we're the second processor, and jump
			* to the secondary_start code if so
			*/
			mfspr r24,SPRN_PIR
			cmpwi r24,0
			bne __secondary_start
			#endif

	/*		/*
	* This is where the main kernel code starts.		* This is where the main kernel code starts.
	*/		*/
	@@ -739,6 +749,9 @@ finish_tlb_load:
	rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */		rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
	#else		#else
	rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */		rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
			#endif
			#ifdef CONFIG_SMP
			ori r12, r12, MAS2_M
	#endif		#endif
	mtspr SPRN_MAS2, r12		mtspr SPRN_MAS2, r12

	@@ -1042,6 +1055,63 @@ _GLOBAL(flush_dcache_L1)

	blr		blr

			#ifdef CONFIG_SMP
			/* When we get here, r24 needs to hold the CPU # */
			.globl __secondary_start
			__secondary_start:
			lis r3,__secondary_hold_acknowledge@h
			ori r3,r3,__secondary_hold_acknowledge@l
			stw r24,0(r3)

			li r3,0
			mr r4,r24 /* Why? */
			bl call_setup_cpu

			lis r3,tlbcam_index@ha
			lwz r3,tlbcam_index@l(r3)
			mtctr r3
			li r26,0 /* r26 safe? */

			/* Load each CAM entry */
			1: mr r3,r26
			bl loadcam_entry
			addi r26,r26,1
			bdnz 1b

			/* get current_thread_info and current */
			lis r1,secondary_ti@ha
			lwz r1,secondary_ti@l(r1)
			lwz r2,TI_TASK(r1)

			/* stack */
			addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
			li r0,0
			stw r0,0(r1)

			/* ptr to current thread */
			addi r4,r2,THREAD /* address of our thread_struct */
			mtspr SPRN_SPRG3,r4

			/* Setup the defaults for TLB entries */
			li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
			mtspr SPRN_MAS4,r4

			/* Jump to start_secondary */
			lis r4,MSR_KERNEL@h
			ori r4,r4,MSR_KERNEL@l
			lis r3,start_secondary@h
			ori r3,r3,start_secondary@l
			mtspr SPRN_SRR0,r3
			mtspr SPRN_SRR1,r4
			sync
			rfi
			sync

			.globl __secondary_hold_acknowledge
			__secondary_hold_acknowledge:
			.long -1
			#endif

	/*		/*
	* We put a few things here that have to be page-aligned. This stuff		* We put a few things here that have to be page-aligned. This stuff
	* goes at the beginning of the data segment, which is page-aligned.		* goes at the beginning of the data segment, which is page-aligned.

arch/powerpc/platforms/85xx/Makefile

+2 −0

Original line number	Original line	Diff line number	Diff line
	#		#
	# Makefile for the PowerPC 85xx linux kernel.		# Makefile for the PowerPC 85xx linux kernel.
	#		#
			obj-$(CONFIG_SMP) += smp.o

	obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o		obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
	obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o		obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
	obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o		obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o

arch/powerpc/platforms/85xx/smp.c

0 → 100644

+104 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Author: Andy Fleming <afleming@freescale.com>
			* Kumar Gala <galak@kernel.crashing.org>
			*
			* Copyright 2006-2008 Freescale Semiconductor Inc.
			*
			* This program is free software; you can redistribute it and/or modify it
			* under the terms of the GNU General Public License as published by the
			* Free Software Foundation; either version 2 of the License, or (at your
			* option) any later version.
			*/

			#include <linux/stddef.h>
			#include <linux/kernel.h>
			#include <linux/init.h>
			#include <linux/delay.h>
			#include <linux/of.h>

			#include <asm/machdep.h>
			#include <asm/pgtable.h>
			#include <asm/page.h>
			#include <asm/mpic.h>
			#include <asm/cacheflush.h>

			#include <sysdev/fsl_soc.h>

			extern volatile unsigned long __secondary_hold_acknowledge;
			extern void __early_start(void);

			#define BOOT_ENTRY_ADDR_UPPER 0
			#define BOOT_ENTRY_ADDR_LOWER 1
			#define BOOT_ENTRY_R3_UPPER 2
			#define BOOT_ENTRY_R3_LOWER 3
			#define BOOT_ENTRY_RESV 4
			#define BOOT_ENTRY_PIR 5
			#define BOOT_ENTRY_R6_UPPER 6
			#define BOOT_ENTRY_R6_LOWER 7
			#define NUM_BOOT_ENTRY 8
			#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))

			static void __init
			smp_85xx_kick_cpu(int nr)
			{
			unsigned long flags;
			const u64 *cpu_rel_addr;
			__iomem u32 *bptr_vaddr;
			struct device_node *np;
			int n = 0;

			WARN_ON (nr < 0 \|\| nr >= NR_CPUS);

			pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);

			local_irq_save(flags);

			np = of_get_cpu_node(nr, NULL);
			cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);

			if (cpu_rel_addr == NULL) {
			printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
			return;
			}

			/* Map the spin table */
			bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);

			out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
			out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));

			/* Wait a bit for the CPU to ack. */
			while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
			mdelay(1);

			iounmap(bptr_vaddr);

			local_irq_restore(flags);

			pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
			}

			static void __init
			smp_85xx_setup_cpu(int cpu_nr)
			{
			mpic_setup_this_cpu();

			/* Clear any pending timer interrupts */
			mtspr(SPRN_TSR, TSR_ENW \| TSR_WIS \| TSR_DIS \| TSR_FIS);

			/* Enable decrementer interrupt */
			mtspr(SPRN_TCR, TCR_DIE);
			}

			struct smp_ops_t smp_85xx_ops = {
			.message_pass = smp_mpic_message_pass,
			.probe = smp_mpic_probe,
			.kick_cpu = smp_85xx_kick_cpu,
			.setup_cpu = smp_85xx_setup_cpu,
			};

			void __init
			mpc85xx_smp_init(void)
			{
			smp_ops = &smp_85xx_ops;
			}