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Commit d5586560 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
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dt-bindings: firmware: Add bindings for Tegra BPMP 



The Boot and Power Management Processor (BPMP) is a co-processor found
in Tegra SoCs. It is designed to handle the early stages of the boot
process as well as to offload power management tasks (such as clocks,
resets, powergates, ...).

The binding document defines the resources that are used by the BPMP
firmware, which implements the interprocessor communication (IPC)
between the CPU and the BPMP.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3dc83674

Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt

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NVIDIA Tegra Boot and Power Management Processor (BPMP)



The BPMP is a specific processor in Tegra chip, which is designed for

booting process handling and offloading the power management, clock

management, and reset control tasks from the CPU. The binding document

defines the resources that would be used by the BPMP firmware driver,

which can create the interprocessor communication (IPC) between the CPU

and BPMP.



Required properties:

- name : Should be bpmp

- compatible

    Array of strings

    One of:

    - "nvidia,tegra186-bpmp"

- mboxes : The phandle of mailbox controller and the mailbox specifier.

- shmem : List of the phandle of the TX and RX shared memory area that

	  the IPC between CPU and BPMP is based on.

- #clock-cells : Should be 1.

- #reset-cells : Should be 1.



This node is a mailbox consumer. See the following files for details of

the mailbox subsystem, and the specifiers implemented by the relevant

provider(s):



- .../mailbox/mailbox.txt

- .../mailbox/nvidia,tegra186-hsp.txt



This node is a clock and reset provider. See the following files for

general documentation of those features, and the specifiers implemented

by this node:



- .../clock/clock-bindings.txt

- <dt-bindings/clock/tegra186-clock.h>

- .../reset/reset.txt

- <dt-bindings/reset/tegra186-reset.h>



The shared memory bindings for BPMP

-----------------------------------



The shared memory area for the IPC TX and RX between CPU and BPMP are

predefined and work on top of sysram, which is an SRAM inside the chip.



See ".../sram/sram.txt" for the bindings.



Example:



hsp_top0: hsp@03c00000 {

	...

	#mbox-cells = <2>;

};



sysram@30000000 {

	compatible = "nvidia,tegra186-sysram", "mmio-sram";

	reg = <0x0 0x30000000 0x0 0x50000>;

	#address-cells = <2>;

	#size-cells = <2>;

	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;



	cpu_bpmp_tx: shmem@4e000 {

		compatible = "nvidia,tegra186-bpmp-shmem";

		reg = <0x0 0x4e000 0x0 0x1000>;

		label = "cpu-bpmp-tx";

		pool;

	};



	cpu_bpmp_rx: shmem@4f000 {

		compatible = "nvidia,tegra186-bpmp-shmem";

		reg = <0x0 0x4f000 0x0 0x1000>;

		label = "cpu-bpmp-rx";

		pool;

	};

};



bpmp {

	compatible = "nvidia,tegra186-bpmp";

	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;

	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};