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Commit d454cecc authored Oct 12, 2017 by Geert Uytterhoeven

clk: renesas: rz: clk-rz is meant for RZ/A1



The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
RZ/G, RZ/N, and RZ/T).  Clarify that the renesas,rz-cpg-clocks DT
bindings and clk-rz driver apply to RZ/A1 only.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>

parent 0022e4a2

Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt

+2 −2

Original line number	Original line	Diff line number	Diff line
	* Renesas RZ Clock Pulse Generator (CPG)		* Renesas RZ/A1 Clock Pulse Generator (CPG)

	The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable		The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
	CPU and GPU clocks, and several fixed ratio dividers.		CPU and GPU clocks, and several fixed ratio dividers.
	The CPG also provides a Clock Domain for SoC devices, in combination with the		The CPG also provides a Clock Domain for SoC devices, in combination with the
	CPG Module Stop (MSTP) Clocks.		CPG Module Stop (MSTP) Clocks.

drivers/clk/renesas/clk-rz.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* rz Core CPG Clocks		* RZ/A1 Core CPG Clocks
	*		*
	* Copyright (C) 2013 Ideas On Board SPRL		* Copyright (C) 2013 Ideas On Board SPRL
	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>		* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>