drm/radeon: split audio enable between eg and r600 (v2) (d3d8c141) · Commits · e / devices / android_kernel_teracube_emerald

drivers/gpu/drm/radeon/dce3_1_afmt.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -165,7 +165,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode m

	/* disable audio prior to setting up hw */		/* disable audio prior to setting up hw */
	dig->afmt->pin = r600_audio_get_pin(rdev);		dig->afmt->pin = r600_audio_get_pin(rdev);
	r600_audio_enable(rdev, dig->afmt->pin, false);		r600_audio_enable(rdev, dig->afmt->pin, 0);

	r600_audio_set_dto(encoder, mode->clock);		r600_audio_set_dto(encoder, mode->clock);

	@@ -240,5 +240,5 @@ void dce3_1_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode m
	r600_hdmi_audio_workaround(encoder);		r600_hdmi_audio_workaround(encoder);

	/* enable audio after to setting up hw */		/* enable audio after to setting up hw */
	r600_audio_enable(rdev, dig->afmt->pin, true);		r600_audio_enable(rdev, dig->afmt->pin, 0xf);
	}		}

drivers/gpu/drm/radeon/dce6_afmt.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -284,13 +284,13 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev)

	void dce6_audio_enable(struct radeon_device *rdev,		void dce6_audio_enable(struct radeon_device *rdev,
	struct r600_audio_pin *pin,		struct r600_audio_pin *pin,
	bool enable)		u8 enable_mask)
	{		{
	if (!pin)		if (!pin)
	return;		return;

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,		WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
	enable ? AUDIO_ENABLED : 0);		enable_mask ? AUDIO_ENABLED : 0);
	}		}

	static const u32 pin_offsets[7] =		static const u32 pin_offsets[7] =

drivers/gpu/drm/radeon/evergreen_hdmi.c

+35 −4

Original line number	Original line	Diff line number	Diff line
	@@ -38,6 +38,37 @@ extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
	extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,		extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
	struct drm_display_mode *mode);		struct drm_display_mode *mode);

			/* enable the audio stream */
			static void dce4_audio_enable(struct radeon_device *rdev,
			struct r600_audio_pin *pin,
			u8 enable_mask)
			{
			u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

			if (!pin)
			return;

			if (enable_mask) {
			tmp \|= AUDIO_ENABLED;
			if (enable_mask & 1)
			tmp \|= PIN0_AUDIO_ENABLED;
			if (enable_mask & 2)
			tmp \|= PIN1_AUDIO_ENABLED;
			if (enable_mask & 4)
			tmp \|= PIN2_AUDIO_ENABLED;
			if (enable_mask & 8)
			tmp \|= PIN3_AUDIO_ENABLED;
			} else {
			tmp &= ~(AUDIO_ENABLED \|
			PIN0_AUDIO_ENABLED \|
			PIN1_AUDIO_ENABLED \|
			PIN2_AUDIO_ENABLED \|
			PIN3_AUDIO_ENABLED);
			}

			WREG32(AZ_HOT_PLUG_CONTROL, tmp);
			}

	/*		/*
	* update the N and CTS parameters for a given pixel clock rate		* update the N and CTS parameters for a given pixel clock rate
	*/		*/
	@@ -318,10 +349,10 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
	/* disable audio prior to setting up hw */		/* disable audio prior to setting up hw */
	if (ASIC_IS_DCE6(rdev)) {		if (ASIC_IS_DCE6(rdev)) {
	dig->afmt->pin = dce6_audio_get_pin(rdev);		dig->afmt->pin = dce6_audio_get_pin(rdev);
	dce6_audio_enable(rdev, dig->afmt->pin, false);		dce6_audio_enable(rdev, dig->afmt->pin, 0);
	} else {		} else {
	dig->afmt->pin = r600_audio_get_pin(rdev);		dig->afmt->pin = r600_audio_get_pin(rdev);
	r600_audio_enable(rdev, dig->afmt->pin, false);		dce4_audio_enable(rdev, dig->afmt->pin, 0);
	}		}

	evergreen_audio_set_dto(encoder, mode->clock);		evergreen_audio_set_dto(encoder, mode->clock);
	@@ -463,9 +494,9 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode

	/* enable audio after to setting up hw */		/* enable audio after to setting up hw */
	if (ASIC_IS_DCE6(rdev))		if (ASIC_IS_DCE6(rdev))
	dce6_audio_enable(rdev, dig->afmt->pin, true);		dce6_audio_enable(rdev, dig->afmt->pin, 1);
	else		else
	r600_audio_enable(rdev, dig->afmt->pin, true);		dce4_audio_enable(rdev, dig->afmt->pin, 0xf);
	}		}

	void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)		void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)

drivers/gpu/drm/radeon/r600_hdmi.c

+23 −14

Original line number	Original line	Diff line number	Diff line
	@@ -163,23 +163,32 @@ void r600_audio_update_hdmi(struct work_struct *work)
	/* enable the audio stream */		/* enable the audio stream */
	void r600_audio_enable(struct radeon_device *rdev,		void r600_audio_enable(struct radeon_device *rdev,
	struct r600_audio_pin *pin,		struct r600_audio_pin *pin,
	bool enable)		u8 enable_mask)
	{		{
	u32 value = 0;		u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

	if (!pin)		if (!pin)
	return;		return;

	if (ASIC_IS_DCE4(rdev)) {		if (enable_mask) {
	if (enable) {		tmp \|= AUDIO_ENABLED;
	value \|= 0x81000000; /* Required to enable audio */		if (enable_mask & 1)
	value \|= 0x0e1000f0; /* fglrx sets that too */		tmp \|= PIN0_AUDIO_ENABLED;
	}		if (enable_mask & 2)
	WREG32(EVERGREEN_AUDIO_ENABLE, value);		tmp \|= PIN1_AUDIO_ENABLED;
			if (enable_mask & 4)
			tmp \|= PIN2_AUDIO_ENABLED;
			if (enable_mask & 8)
			tmp \|= PIN3_AUDIO_ENABLED;
	} else {		} else {
	WREG32_P(R600_AUDIO_ENABLE,		tmp &= ~(AUDIO_ENABLED \|
	enable ? 0x81000000 : 0x0, ~0x81000000);		PIN0_AUDIO_ENABLED \|
			PIN1_AUDIO_ENABLED \|
			PIN2_AUDIO_ENABLED \|
			PIN3_AUDIO_ENABLED);
	}		}

			WREG32(AZ_HOT_PLUG_CONTROL, tmp);
	}		}

	/*		/*
	@@ -200,7 +209,7 @@ int r600_audio_init(struct radeon_device *rdev)
	rdev->audio.pin[0].category_code = 0;		rdev->audio.pin[0].category_code = 0;
	rdev->audio.pin[0].id = 0;		rdev->audio.pin[0].id = 0;
	/* disable audio. it will be set up later */		/* disable audio. it will be set up later */
	r600_audio_enable(rdev, &rdev->audio.pin[0], false);		r600_audio_enable(rdev, &rdev->audio.pin[0], 0);

	return 0;		return 0;
	}		}
	@@ -214,7 +223,7 @@ void r600_audio_fini(struct radeon_device *rdev)
	if (!rdev->audio.enabled)		if (!rdev->audio.enabled)
	return;		return;

	r600_audio_enable(rdev, &rdev->audio.pin[0], false);		r600_audio_enable(rdev, &rdev->audio.pin[0], 0);

	rdev->audio.enabled = false;		rdev->audio.enabled = false;
	}		}
	@@ -511,7 +520,7 @@ void r600_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mod

	/* disable audio prior to setting up hw */		/* disable audio prior to setting up hw */
	dig->afmt->pin = r600_audio_get_pin(rdev);		dig->afmt->pin = r600_audio_get_pin(rdev);
	r600_audio_enable(rdev, dig->afmt->pin, false);		r600_audio_enable(rdev, dig->afmt->pin, 0xf);

	r600_audio_set_dto(encoder, mode->clock);		r600_audio_set_dto(encoder, mode->clock);

	@@ -597,7 +606,7 @@ void r600_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mod
	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);		WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);

	/* enable audio after to setting up hw */		/* enable audio after to setting up hw */
	r600_audio_enable(rdev, dig->afmt->pin, true);		r600_audio_enable(rdev, dig->afmt->pin, 0xf);
	}		}

	/**		/**

drivers/gpu/drm/radeon/r600d.h

+17 −0

Original line number	Original line	Diff line number	Diff line
	@@ -934,6 +934,23 @@
	# define TARGET_LINK_SPEED_MASK (0xf << 0)		# define TARGET_LINK_SPEED_MASK (0xf << 0)
	# define SELECTABLE_DEEMPHASIS (1 << 6)		# define SELECTABLE_DEEMPHASIS (1 << 6)

			/* Audio */
			#define AZ_HOT_PLUG_CONTROL 0x7300
			# define AZ_FORCE_CODEC_WAKE (1 << 0)
			# define JACK_DETECTION_ENABLE (1 << 4)
			# define UNSOLICITED_RESPONSE_ENABLE (1 << 8)
			# define CODEC_HOT_PLUG_ENABLE (1 << 12)
			# define AUDIO_ENABLED (1 << 31)
			/* DCE3 adds */
			# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
			# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
			# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
			# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
			# define PIN0_AUDIO_ENABLED (1 << 24)
			# define PIN1_AUDIO_ENABLED (1 << 25)
			# define PIN2_AUDIO_ENABLED (1 << 26)
			# define PIN3_AUDIO_ENABLED (1 << 27)

	/* Audio clocks DCE 2.0/3.0 */		/* Audio clocks DCE 2.0/3.0 */
	#define AUDIO_DTO 0x7340		#define AUDIO_DTO 0x7340
	# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)		# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)