Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d2212bc7 authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Add missing IDs for newer cpus. 



Also, the us3_cpufreq driver can work on Ultra-IV and IV+.
They use the SAFARI bus register to control the clock divider
just like Ultra-III and III+ do.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f16af555

arch/sparc64/kernel/cpu.c

+4 −0
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@ struct cpu_fp_info linux_sparc_fpu[] = { 
  { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},

  { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},

  { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},

  { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},

  { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},

};



#define NSPARCFPU  (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
@@ -53,6 +55,8 @@ struct cpu_iu_info linux_sparc_chips[] = { 
  { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},

  { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},

  { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},

  { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},

  { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},

};



#define NSPARCCHIPS  (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))

arch/sparc64/kernel/us3_cpufreq.c

+4 −1
Original line number Diff line number Diff line
@@ -208,7 +208,10 @@ static int __init us3_freq_init(void) 
	impl  = ((ver >> 32) & 0xffff);



	if (manuf == CHEETAH_MANUF &&

	    (impl == CHEETAH_IMPL || impl == CHEETAH_PLUS_IMPL)) {

	    (impl == CHEETAH_IMPL ||

	     impl == CHEETAH_PLUS_IMPL ||

	     impl == JAGUAR_IMPL ||

	     impl == PANTHER_IMPL)) {

		struct cpufreq_driver *driver;



		ret = -ENOMEM;

include/asm-sparc64/head.h

+6 −3
Original line number Diff line number Diff line
@@ -12,9 +12,12 @@ 
#define __JALAPENO_ID	0x003e0016



#define CHEETAH_MANUF		0x003e

#define CHEETAH_IMPL		0x0014

#define CHEETAH_PLUS_IMPL	0x0015

#define JALAPENO_IMPL		0x0016

#define CHEETAH_IMPL		0x0014 /* Ultra-III   */

#define CHEETAH_PLUS_IMPL	0x0015 /* Ultra-III+  */

#define JALAPENO_IMPL		0x0016 /* Ultra-IIIi  */

#define JAGUAR_IMPL		0x0018 /* Ultra-IV    */

#define PANTHER_IMPL		0x0019 /* Ultra-IV+   */

#define SERRANO_IMPL		0x0022 /* Ultra-IIIi+ */



#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label)	\

	rdpr	%ver, %tmp1;			\