Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d20ced23 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'dt/irq-fix' into fixes 

* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger
parents 7ccb8e63 f2a89d3b

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -255,10 +255,10 @@ 
		/* Local timer */

		/* Local timer */

		timer {

		timer {

			compatible = "arm,armv8-timer";

			compatible = "arm,armv8-timer";

			interrupts = <1 13 0xf01>,

			interrupts = <1 13 0xf08>,

				     <1 14 0xf01>,

				     <1 14 0xf08>,

				     <1 11 0xf01>,

				     <1 11 0xf08>,

				     <1 10 0xf01>;

				     <1 10 0xf08>;

		};

		};





		timer0: timer0@ffc03000 {

		timer0: timer0@ffc03000 {

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -102,13 +102,13 @@ 
	timer {

	timer {

		compatible = "arm,armv8-timer";

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

			     <GIC_PPI 14

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

			     <GIC_PPI 11

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

			     <GIC_PPI 10

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;

	};

	};





	xtal: xtal-clk {

	xtal: xtal-clk {

arch/arm64/boot/dts/apm/apm-storm.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -110,10 +110,10 @@ 




	timer {

	timer {

		compatible = "arm,armv8-timer";

		compatible = "arm,armv8-timer";

		interrupts = <1 0 0xff01>,	/* Secure Phys IRQ */

		interrupts = <1 0 0xff08>,	/* Secure Phys IRQ */

			     <1 13 0xff01>,	/* Non-secure Phys IRQ */

			     <1 13 0xff08>,	/* Non-secure Phys IRQ */

			     <1 14 0xff01>,	/* Virt IRQ */

			     <1 14 0xff08>,	/* Virt IRQ */

			     <1 15 0xff01>;	/* Hyp IRQ */

			     <1 15 0xff08>;	/* Hyp IRQ */

		clock-frequency = <50000000>;

		clock-frequency = <50000000>;

	};

	};

arch/arm64/boot/dts/broadcom/ns2.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -88,13 +88,13 @@ 
	timer {

	timer {

		compatible = "arm,armv8-timer";

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |

			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |

			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>,

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |

			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |

			      IRQ_TYPE_EDGE_RISING)>;

			      IRQ_TYPE_LEVEL_LOW)>;

	};

	};





	pmu {

	pmu {

arch/arm64/boot/dts/cavium/thunder-88xx.dtsi

+4 −4
Original line number Original line Diff line number Diff line
@@ -354,10 +354,10 @@ 




	timer {

	timer {

		compatible = "arm,armv8-timer";

		compatible = "arm,armv8-timer";

		interrupts = <1 13 0xff01>,

		interrupts = <1 13 4>,

		             <1 14 0xff01>,

		             <1 14 4>,

		             <1 11 0xff01>,

		             <1 11 4>,

		             <1 10 0xff01>;

		             <1 10 4>;

	};

	};





	pmu {

	pmu {