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Commit d0e62855 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu: add uvd enc registers in header 



Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4b6aca2f

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

+15 −0
Original line number Diff line number Diff line
@@ -36,6 +36,16 @@ 
#define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5

#define mmUVD_POWER_STATUS_U                                                    0x3bfd

#define mmUVD_NO_OP                                                             0x3bff

#define mmUVD_RB_BASE_LO2                                                       0x3c21

#define mmUVD_RB_BASE_HI2                                                       0x3c22

#define mmUVD_RB_SIZE2                                                          0x3c23

#define mmUVD_RB_RPTR2                                                          0x3c24

#define mmUVD_RB_WPTR2                                                          0x3c25

#define mmUVD_RB_BASE_LO                                                        0x3c26

#define mmUVD_RB_BASE_HI                                                        0x3c27

#define mmUVD_RB_SIZE                                                           0x3c28

#define mmUVD_RB_RPTR                                                           0x3c29

#define mmUVD_RB_WPTR                                                           0x3c2a

#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                          0x3c69

#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                         0x3c68

#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                          0x3c67
@@ -43,6 +53,11 @@ 
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                      0x3c5f

#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                     0x3c5e

#define mmUVD_SEMA_CNTL                                                         0x3d00

#define mmUVD_RB_WPTR3                                                          0x3d1c

#define mmUVD_RB_RPTR3                                                          0x3d1b

#define mmUVD_RB_BASE_LO3                                                       0x3d1d

#define mmUVD_RB_BASE_HI3                                                       0x3d1e

#define mmUVD_RB_SIZE3                                                          0x3d1f

#define mmUVD_LMI_EXT40_ADDR                                                    0x3d26

#define mmUVD_CTX_INDEX                                                         0x3d28

#define mmUVD_CTX_DATA                                                          0x3d29