Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cfed4409 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: BF54x: punt useless "masks" for count/address MMRs 



There's no point in having mask defines when the entire MMR value is a
count or address.  i.e. applying a mask of -1 is pointless.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent e153a97c

arch/blackfin/mach-bf548/include/mach/defBF54x_base.h

+0 −104
Original line number Diff line number Diff line
@@ -1815,10 +1815,6 @@ 
#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */

#define               CORE_MERROR  0x80       /* Core Error (2nd) */



/* Bit masks for EBIU_ERRADD */



#define             ERROR_ADDRESS  0xffffffff /* Error Address */



/* Bit masks for EBIU_RSTCTL */



#define                 DDRSRESET  0x1        /* DDR soft reset */
@@ -1827,98 +1823,6 @@ 
#define                     SRACK  0x10       /* Self-refresh acknowledge */

#define                MDDRENABLE  0x20       /* Mobile DDR enable */



/* Bit masks for EBIU_DDRBRC0 */



#define                      BRC0  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC1 */



#define                      BRC1  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC2 */



#define                      BRC2  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC3 */



#define                      BRC3  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC4 */



#define                      BRC4  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC5 */



#define                      BRC5  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC6 */



#define                      BRC6  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBRC7 */



#define                      BRC7  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC0 */



#define                      BWC0  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC1 */



#define                      BWC1  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC2 */



#define                      BWC2  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC3 */



#define                      BWC3  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC4 */



#define                      BWC4  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC5 */



#define                      BWC5  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC6 */



#define                      BWC6  0xffffffff /* Count */



/* Bit masks for EBIU_DDRBWC7 */



#define                      BWC7  0xffffffff /* Count */



/* Bit masks for EBIU_DDRACCT */



#define                      ACCT  0xffffffff /* Count */



/* Bit masks for EBIU_DDRTACT */



#define                      TECT  0xffffffff /* Count */



/* Bit masks for EBIU_DDRARCT */



#define                      ARCT  0xffffffff /* Count */



/* Bit masks for EBIU_DDRGC0 */



#define                       GC0  0xffffffff /* Count */



/* Bit masks for EBIU_DDRGC1 */



#define                       GC1  0xffffffff /* Count */



/* Bit masks for EBIU_DDRGC2 */



#define                       GC2  0xffffffff /* Count */



/* Bit masks for EBIU_DDRGC3 */



#define                       GC3  0xffffffff /* Count */



/* Bit masks for EBIU_DDRMCEN */



#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
@@ -2408,14 +2312,6 @@ 
#define                      UCCT  0x40       /* Universal Counter CAN Trigger */

#define                       UCE  0x80       /* Universal Counter Enable */



/* Bit masks for CAN0_UCCNT */



#define                     UCCNT  0xffff     /* Universal Counter Count Value */



/* Bit masks for CAN0_UCRC */



#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */



/* Bit masks for CAN0_CEC */



#define                    RXECNT  0xff       /* Receive Error Counter */