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Commit cf6824ac authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: dc: Move register definitions into a table 



After commit 67e04d1a ("drm/tegra: dc: Trace register accesses"),
the debugfs register dump implementation causes excessive stack usage
and can result in build warnings. To fix this, move the register
definitions into a table and iterate over the table while dumping the
registers to debugfs.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 91cc0706

drivers/gpu/drm/tegra/dc.c

+224 −218
Original line number Diff line number Diff line
@@ -1383,10 +1383,228 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) 
	return IRQ_HANDLED;

}



#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }



static const struct debugfs_reg32 tegra_dc_regs[] = {

	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),

	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),

	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),

	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),

	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),

	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),

	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),

	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),

	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),

	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),

	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),

	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),

	DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),

	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),

	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),

	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),

	DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),

	DEBUGFS_REG32(DC_CMD_INT_STATUS),

	DEBUGFS_REG32(DC_CMD_INT_MASK),

	DEBUGFS_REG32(DC_CMD_INT_ENABLE),

	DEBUGFS_REG32(DC_CMD_INT_TYPE),

	DEBUGFS_REG32(DC_CMD_INT_POLARITY),

	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),

	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),

	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),

	DEBUGFS_REG32(DC_CMD_STATE_ACCESS),

	DEBUGFS_REG32(DC_CMD_STATE_CONTROL),

	DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),

	DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),

	DEBUGFS_REG32(DC_COM_CRC_CONTROL),

	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),

	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),

	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),

	DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),

	DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),

	DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),

	DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),

	DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),

	DEBUGFS_REG32(DC_COM_SPI_CONTROL),

	DEBUGFS_REG32(DC_COM_SPI_START_BYTE),

	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),

	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),

	DEBUGFS_REG32(DC_COM_HSPI_CS_DC),

	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),

	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),

	DEBUGFS_REG32(DC_COM_GPIO_CTRL),

	DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),

	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),

	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),

	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),

	DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),

	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),

	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),

	DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),

	DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),

	DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),

	DEBUGFS_REG32(DC_DISP_BACK_PORCH),

	DEBUGFS_REG32(DC_DISP_ACTIVE),

	DEBUGFS_REG32(DC_DISP_FRONT_PORCH),

	DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),

	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),

	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),

	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),

	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),

	DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),

	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),

	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),

	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),

	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),

	DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),

	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),

	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),

	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),

	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),

	DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),

	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),

	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),

	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),

	DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),

	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),

	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),

	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),

	DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),

	DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),

	DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),

	DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),

	DEBUGFS_REG32(DC_DISP_M0_CONTROL),

	DEBUGFS_REG32(DC_DISP_M1_CONTROL),

	DEBUGFS_REG32(DC_DISP_DI_CONTROL),

	DEBUGFS_REG32(DC_DISP_PP_CONTROL),

	DEBUGFS_REG32(DC_DISP_PP_SELECT_A),

	DEBUGFS_REG32(DC_DISP_PP_SELECT_B),

	DEBUGFS_REG32(DC_DISP_PP_SELECT_C),

	DEBUGFS_REG32(DC_DISP_PP_SELECT_D),

	DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),

	DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),

	DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),

	DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),

	DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),

	DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),

	DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),

	DEBUGFS_REG32(DC_DISP_BORDER_COLOR),

	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),

	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),

	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),

	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),

	DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),

	DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),

	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),

	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),

	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),

	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),

	DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),

	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),

	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),

	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),

	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),

	DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),

	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),

	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),

	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),

	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),

	DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),

	DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),

	DEBUGFS_REG32(DC_DISP_SD_CONTROL),

	DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),

	DEBUGFS_REG32(DC_DISP_SD_LUT(0)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(1)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(2)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(3)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(4)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(5)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(6)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(7)),

	DEBUGFS_REG32(DC_DISP_SD_LUT(8)),

	DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),

	DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),

	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),

	DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),

	DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),

	DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),

	DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),

	DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),

	DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),

	DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),

	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),

	DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),

	DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),

	DEBUGFS_REG32(DC_WIN_BYTE_SWAP),

	DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),

	DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),

	DEBUGFS_REG32(DC_WIN_POSITION),

	DEBUGFS_REG32(DC_WIN_SIZE),

	DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),

	DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),

	DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),

	DEBUGFS_REG32(DC_WIN_DDA_INC),

	DEBUGFS_REG32(DC_WIN_LINE_STRIDE),

	DEBUGFS_REG32(DC_WIN_BUF_STRIDE),

	DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),

	DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),

	DEBUGFS_REG32(DC_WIN_DV_CONTROL),

	DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),

	DEBUGFS_REG32(DC_WIN_BLEND_1WIN),

	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),

	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),

	DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),

	DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),

	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),

	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),

	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),

	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),

	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),

	DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),

	DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),

	DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),

	DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),

};



static int tegra_dc_show_regs(struct seq_file *s, void *data)

{

	struct drm_info_node *node = s->private;

	struct tegra_dc *dc = node->info_ent->data;

	unsigned int i;

	int err = 0;



	drm_modeset_lock(&dc->base.mutex, NULL);
@@ -1396,224 +1614,12 @@ static int tegra_dc_show_regs(struct seq_file *s, void *data) 
		goto unlock;

	}



#define DUMP_REG(name)						\

	seq_printf(s, "%-40s %#05x %08x\n", #name, name,	\

		   tegra_dc_readl(dc, name))



	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);

	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);

	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);

	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);

	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);

	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);

	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);

	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);

	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);

	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);

	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);

	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);

	DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);

	DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);

	DUMP_REG(DC_CMD_DISPLAY_COMMAND);

	DUMP_REG(DC_CMD_SIGNAL_RAISE);

	DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);

	DUMP_REG(DC_CMD_INT_STATUS);

	DUMP_REG(DC_CMD_INT_MASK);

	DUMP_REG(DC_CMD_INT_ENABLE);

	DUMP_REG(DC_CMD_INT_TYPE);

	DUMP_REG(DC_CMD_INT_POLARITY);

	DUMP_REG(DC_CMD_SIGNAL_RAISE1);

	DUMP_REG(DC_CMD_SIGNAL_RAISE2);

	DUMP_REG(DC_CMD_SIGNAL_RAISE3);

	DUMP_REG(DC_CMD_STATE_ACCESS);

	DUMP_REG(DC_CMD_STATE_CONTROL);

	DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);

	DUMP_REG(DC_CMD_REG_ACT_CONTROL);

	DUMP_REG(DC_COM_CRC_CONTROL);

	DUMP_REG(DC_COM_CRC_CHECKSUM);

	DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));

	DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));

	DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));

	DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));

	DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));

	DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));

	DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));

	DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));

	DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));

	DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));

	DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));

	DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));

	DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));

	DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));

	DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));

	DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));

	DUMP_REG(DC_COM_PIN_INPUT_DATA(0));

	DUMP_REG(DC_COM_PIN_INPUT_DATA(1));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));

	DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));

	DUMP_REG(DC_COM_PIN_MISC_CONTROL);

	DUMP_REG(DC_COM_PIN_PM0_CONTROL);

	DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);

	DUMP_REG(DC_COM_PIN_PM1_CONTROL);

	DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);

	DUMP_REG(DC_COM_SPI_CONTROL);

	DUMP_REG(DC_COM_SPI_START_BYTE);

	DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);

	DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);

	DUMP_REG(DC_COM_HSPI_CS_DC);

	DUMP_REG(DC_COM_SCRATCH_REGISTER_A);

	DUMP_REG(DC_COM_SCRATCH_REGISTER_B);

	DUMP_REG(DC_COM_GPIO_CTRL);

	DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);

	DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);

	DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);

	DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);

	DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);

	DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);

	DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);

	DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);

	DUMP_REG(DC_DISP_REF_TO_SYNC);

	DUMP_REG(DC_DISP_SYNC_WIDTH);

	DUMP_REG(DC_DISP_BACK_PORCH);

	DUMP_REG(DC_DISP_ACTIVE);

	DUMP_REG(DC_DISP_FRONT_PORCH);

	DUMP_REG(DC_DISP_H_PULSE0_CONTROL);

	DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);

	DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);

	DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);

	DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);

	DUMP_REG(DC_DISP_H_PULSE1_CONTROL);

	DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);

	DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);

	DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);

	DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);

	DUMP_REG(DC_DISP_H_PULSE2_CONTROL);

	DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);

	DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);

	DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);

	DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);

	DUMP_REG(DC_DISP_V_PULSE0_CONTROL);

	DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);

	DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);

	DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);

	DUMP_REG(DC_DISP_V_PULSE1_CONTROL);

	DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);

	DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);

	DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);

	DUMP_REG(DC_DISP_V_PULSE2_CONTROL);

	DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);

	DUMP_REG(DC_DISP_V_PULSE3_CONTROL);

	DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);

	DUMP_REG(DC_DISP_M0_CONTROL);

	DUMP_REG(DC_DISP_M1_CONTROL);

	DUMP_REG(DC_DISP_DI_CONTROL);

	DUMP_REG(DC_DISP_PP_CONTROL);

	DUMP_REG(DC_DISP_PP_SELECT_A);

	DUMP_REG(DC_DISP_PP_SELECT_B);

	DUMP_REG(DC_DISP_PP_SELECT_C);

	DUMP_REG(DC_DISP_PP_SELECT_D);

	DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);

	DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);

	DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);

	DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);

	DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);

	DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);

	DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);

	DUMP_REG(DC_DISP_BORDER_COLOR);

	DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);

	DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);

	DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);

	DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);

	DUMP_REG(DC_DISP_CURSOR_FOREGROUND);

	DUMP_REG(DC_DISP_CURSOR_BACKGROUND);

	DUMP_REG(DC_DISP_CURSOR_START_ADDR);

	DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);

	DUMP_REG(DC_DISP_CURSOR_POSITION);

	DUMP_REG(DC_DISP_CURSOR_POSITION_NS);

	DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);

	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);

	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);

	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);

	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);

	DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);

	DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);

	DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);

	DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);

	DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);

	DUMP_REG(DC_DISP_DAC_CRT_CTRL);

	DUMP_REG(DC_DISP_DISP_MISC_CONTROL);

	DUMP_REG(DC_DISP_SD_CONTROL);

	DUMP_REG(DC_DISP_SD_CSC_COEFF);

	DUMP_REG(DC_DISP_SD_LUT(0));

	DUMP_REG(DC_DISP_SD_LUT(1));

	DUMP_REG(DC_DISP_SD_LUT(2));

	DUMP_REG(DC_DISP_SD_LUT(3));

	DUMP_REG(DC_DISP_SD_LUT(4));

	DUMP_REG(DC_DISP_SD_LUT(5));

	DUMP_REG(DC_DISP_SD_LUT(6));

	DUMP_REG(DC_DISP_SD_LUT(7));

	DUMP_REG(DC_DISP_SD_LUT(8));

	DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);

	DUMP_REG(DC_DISP_DC_PIXEL_COUNT);

	DUMP_REG(DC_DISP_SD_HISTOGRAM(0));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(1));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(2));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(3));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(4));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(5));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(6));

	DUMP_REG(DC_DISP_SD_HISTOGRAM(7));

	DUMP_REG(DC_DISP_SD_BL_TF(0));

	DUMP_REG(DC_DISP_SD_BL_TF(1));

	DUMP_REG(DC_DISP_SD_BL_TF(2));

	DUMP_REG(DC_DISP_SD_BL_TF(3));

	DUMP_REG(DC_DISP_SD_BL_CONTROL);

	DUMP_REG(DC_DISP_SD_HW_K_VALUES);

	DUMP_REG(DC_DISP_SD_MAN_K_VALUES);

	DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);

	DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);

	DUMP_REG(DC_WIN_WIN_OPTIONS);

	DUMP_REG(DC_WIN_BYTE_SWAP);

	DUMP_REG(DC_WIN_BUFFER_CONTROL);

	DUMP_REG(DC_WIN_COLOR_DEPTH);

	DUMP_REG(DC_WIN_POSITION);

	DUMP_REG(DC_WIN_SIZE);

	DUMP_REG(DC_WIN_PRESCALED_SIZE);

	DUMP_REG(DC_WIN_H_INITIAL_DDA);

	DUMP_REG(DC_WIN_V_INITIAL_DDA);

	DUMP_REG(DC_WIN_DDA_INC);

	DUMP_REG(DC_WIN_LINE_STRIDE);

	DUMP_REG(DC_WIN_BUF_STRIDE);

	DUMP_REG(DC_WIN_UV_BUF_STRIDE);

	DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);

	DUMP_REG(DC_WIN_DV_CONTROL);

	DUMP_REG(DC_WIN_BLEND_NOKEY);

	DUMP_REG(DC_WIN_BLEND_1WIN);

	DUMP_REG(DC_WIN_BLEND_2WIN_X);

	DUMP_REG(DC_WIN_BLEND_2WIN_Y);

	DUMP_REG(DC_WIN_BLEND_3WIN_XY);

	DUMP_REG(DC_WIN_HP_FETCH_CONTROL);

	DUMP_REG(DC_WINBUF_START_ADDR);

	DUMP_REG(DC_WINBUF_START_ADDR_NS);

	DUMP_REG(DC_WINBUF_START_ADDR_U);

	DUMP_REG(DC_WINBUF_START_ADDR_U_NS);

	DUMP_REG(DC_WINBUF_START_ADDR_V);

	DUMP_REG(DC_WINBUF_START_ADDR_V_NS);

	DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);

	DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);

	DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);

	DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);

	DUMP_REG(DC_WINBUF_UFLOW_STATUS);

	DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);

	DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);

	DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);



#undef DUMP_REG

	for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {

		unsigned int offset = tegra_dc_regs[i].offset;



		seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,

			   offset, tegra_dc_readl(dc, offset));

	}



unlock:

	drm_modeset_unlock(&dc->base.mutex);