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Commit cf2fbdd2 authored Mar 16, 2013 by Masanari Iida Committed by Jiri Kosina Mar 18, 2013

treewide: Fix typos in printk and comment



Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

parent ce03cb20

arch/arc/plat-arcfpga/Kconfig

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -53,7 +53,7 @@ menuconfig ARC_HAS_BVCI_LAT_UNIT
	bool "BVCI Bus Latency Unit"		bool "BVCI Bus Latency Unit"
	depends on ARC_BOARD_ML509 \|\| ARC_BOARD_ANGEL4		depends on ARC_BOARD_ML509 \|\| ARC_BOARD_ANGEL4
	help		help
	IP to add artifical latency to BVCI Bus Based FPGA builds.		IP to add artificial latency to BVCI Bus Based FPGA builds.
	The default latency (even worst case) for FPGA is non-realistic		The default latency (even worst case) for FPGA is non-realistic
	(~10 SDRAM, ~5 SSRAM).		(~10 SDRAM, ~5 SSRAM).

arch/blackfin/include/asm/bfin_sport3.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -41,7 +41,7 @@
	#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */		#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
	#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */		#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
	#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */		#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
	#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */		#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */
	#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */		#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
	#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */		#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
	#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */		#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */

arch/s390/kernel/irq.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -33,7 +33,7 @@ struct irq_class {
	};		};

	/*		/*
	* The list of "main" irq classes on s390. This is the list of interrrupts		* The list of "main" irq classes on s390. This is the list of interrupts
	* that appear both in /proc/stat ("intr" line) and /proc/interrupts.		* that appear both in /proc/stat ("intr" line) and /proc/interrupts.
	* Historically only external and I/O interrupts have been part of /proc/stat.		* Historically only external and I/O interrupts have been part of /proc/stat.
	* We can't add the split external and I/O sub classes since the first field		* We can't add the split external and I/O sub classes since the first field

arch/s390/kvm/trace.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -67,7 +67,7 @@ TRACE_EVENT(kvm_s390_sie_fault,
	#define sie_intercept_code \		#define sie_intercept_code \
	{0x04, "Instruction"}, \		{0x04, "Instruction"}, \
	{0x08, "Program interruption"}, \		{0x08, "Program interruption"}, \
	{0x0C, "Instruction and program interuption"}, \		{0x0C, "Instruction and program interruption"}, \
	{0x10, "External request"}, \		{0x10, "External request"}, \
	{0x14, "External interruption"}, \		{0x14, "External interruption"}, \
	{0x18, "I/O request"}, \		{0x18, "I/O request"}, \

drivers/crypto/caam/ctrl.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -66,7 +66,7 @@ static void build_instantiation_desc(u32 *desc)

	/*		/*
	* load 1 to clear written reg:		* load 1 to clear written reg:
	* resets the done interrrupt and returns the RNG to idle.		* resets the done interrupt and returns the RNG to idle.
	*/		*/
	append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);		append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);