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Unverified Commit ce571b80 authored by Bard Liao's avatar Bard Liao Committed by Mark Brown
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ASoC: rt5659: Separate adc 1/2 clock control 



The control bits of ADC 1 and 2 clock are different. We have to
separate it.

Signed-off-by: default avatarZhong An <zhongan@pinecone.net>
Signed-off-by: default avatarBard Liao <bardliao@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 50b12308

sound/soc/codecs/rt5659.c

+32 −6
Original line number Diff line number Diff line
@@ -1622,7 +1622,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w, 
	return idx;

}



static int set_adc_clk(struct snd_soc_dapm_widget *w,

static int set_adc1_clk(struct snd_soc_dapm_widget *w,

	struct snd_kcontrol *kcontrol, int event)

{

	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
@@ -1630,13 +1630,39 @@ static int set_adc_clk(struct snd_soc_dapm_widget *w, 
	switch (event) {

	case SND_SOC_DAPM_POST_PMU:

		snd_soc_component_update_bits(component, RT5659_CHOP_ADC,

			RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK,

			RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK);

			RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK,

			RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK);

		break;



	case SND_SOC_DAPM_PRE_PMD:

		snd_soc_component_update_bits(component, RT5659_CHOP_ADC,

			RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, 0);

			RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 0);

		break;



	default:

		return 0;

	}



	return 0;



}



static int set_adc2_clk(struct snd_soc_dapm_widget *w,

	struct snd_kcontrol *kcontrol, int event)

{

	struct snd_soc_component *component =

		snd_soc_dapm_to_component(w->dapm);



	switch (event) {

	case SND_SOC_DAPM_POST_PMU:

		snd_soc_component_update_bits(component, RT5659_CHOP_ADC,

			RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK,

			RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK);

		break;



	case SND_SOC_DAPM_PRE_PMD:

		snd_soc_component_update_bits(component, RT5659_CHOP_ADC,

			RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 0);

		break;



	default:
@@ -2559,9 +2585,9 @@ static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = { 
		RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1,

		RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,

	SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc1_clk,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,

	SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc2_clk,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),



	/* ADC Mux */

sound/soc/codecs/rt5659.h

+8 −4
Original line number Diff line number Diff line
@@ -1743,10 +1743,14 @@ 
#define RT5659_CKGEN_DAC2_SFT			4



/* Chopper and Clock control for ADC (0x013b)*/

#define RT5659_CKXEN_ADCC_MASK			(0x1 << 13)

#define RT5659_CKXEN_ADCC_SFT			13

#define RT5659_CKGEN_ADCC_MASK			(0x1 << 12)

#define RT5659_CKGEN_ADCC_SFT			12

#define RT5659_CKXEN_ADC1_MASK			(0x1 << 13)

#define RT5659_CKXEN_ADC1_SFT			13

#define RT5659_CKGEN_ADC1_MASK			(0x1 << 12)

#define RT5659_CKGEN_ADC1_SFT			12

#define RT5659_CKXEN_ADC2_MASK			(0x1 << 5)

#define RT5659_CKXEN_ADC2_SFT			5

#define RT5659_CKGEN_ADC2_MASK			(0x1 << 4)

#define RT5659_CKGEN_ADC2_SFT			4



/* Test Mode Control 1 (0x0145) */

#define RT5659_AD2DA_LB_MASK			(0x1 << 9)