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Commit ce1d3fde authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "This update brings:

   - the big cleanup up by Maxime for device control and slave
     capabilities.  This makes the API much cleaner.

   - new IMG MDC driver by Andrew

   - new Renesas R-Car Gen2 DMA Controller driver by Laurent along with
     bunch of fixes on rcar drivers

   - odd fixes and updates spread over driver"

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (130 commits)
  dmaengine: pl330: add DMA_PAUSE feature
  dmaengine: pl330: improve pl330_tx_status() function
  dmaengine: rcar-dmac: Disable channel 0 when using IOMMU
  dmaengine: rcar-dmac: Work around descriptor mode IOMMU errata
  dmaengine: rcar-dmac: Allocate hardware descriptors with DMAC device
  dmaengine: rcar-dmac: Fix oops due to unintialized list in error ISR
  dmaengine: rcar-dmac: Fix spinlock issues in interrupt
  dmaenegine: edma: fix sparse warnings
  dmaengine: rcar-dmac: Fix uninitialized variable usage
  dmaengine: shdmac: extend PM methods
  dmaengine: shdmac: use SET_RUNTIME_PM_OPS()
  dmaengine: pl330: fix bug that cause start the same descs in cyclic
  dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers
  dmaengine: at_xdmac: simplify channel configuration stuff
  dmaengine: at_xdmac: introduce save_cc field
  dmaengine: at_xdmac: wait for in-progress transaction to complete after pausing a channel
  ioat: fail self-test if wait_for_completion times out
  dmaengine: dw: define DW_DMA_MAX_NR_MASTERS
  dmaengine: dw: amend description of dma_dev field
  dmatest: move src_off, dst_off, len inside loop
  ...
parents 928fce2f 88987d2c

Documentation/devicetree/bindings/dma/img-mdc-dma.txt

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* IMG Multi-threaded DMA Controller (MDC)



Required properties:

- compatible: Must be "img,pistachio-mdc-dma".

- reg: Must contain the base address and length of the MDC registers.

- interrupts: Must contain all the per-channel DMA interrupts.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clock/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - sys: MDC system interface clock.

- img,cr-periph: Must contain a phandle to the peripheral control syscon

  node which contains the DMA request to channel mapping registers.

- img,max-burst-multiplier: Must be the maximum supported burst size multiplier.

  The maximum burst size is this value multiplied by the hardware-reported bus

  width.

- #dma-cells: Must be 3:

  - The first cell is the peripheral's DMA request line.

  - The second cell is a bitmap specifying to which channels the DMA request

    line may be mapped (i.e. bit N set indicates channel N is usable).

  - The third cell is the thread ID to be used by the channel.



Optional properties:

- dma-channels: Number of supported DMA channels, up to 32.  If not specified

  the number reported by the hardware is used.



Example:



mdc: dma-controller@18143000 {

	compatible = "img,pistachio-mdc-dma";

	reg = <0x18143000 0x1000>;

	interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&system_clk>;

	clock-names = "sys";



	img,max-burst-multiplier = <16>;

	img,cr-periph = <&cr_periph>;



	#dma-cells = <3>;

};



spi@18100f00 {

	...

	dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;

	dma-names = "tx", "rx";

	...

};

Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

+0 −3
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@@ -5,9 +5,6 @@ controller instances named DMAC capable of serving multiple clients. Channels 
can be dedicated to specific clients or shared between a large number of

clients.



DMA clients are connected to the DMAC ports referenced by an 8-bit identifier

called MID/RID.



Each DMA client is connected to one dedicated port of the DMAC, identified by

an 8-bit port number called the MID/RID. A DMA controller can thus serve up to

256 clients in total. When the number of hardware channels is lower than the

Documentation/devicetree/bindings/dma/snps-dma.txt

+1 −1
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ Example: 
		chan_allocation_order = <1>;

		chan_priority = <1>;

		block_size = <0xfff>;

		data_width = <3 3 0 0>;

		data_width = <3 3>;

	};



DMA clients connected to the Designware DMA controller must use the format

Documentation/dmaengine/provider.txt

+55 −42
Original line number Diff line number Diff line
@@ -113,6 +113,31 @@ need to initialize a few fields in there: 
  * channels:	should be initialized as a list using the

		INIT_LIST_HEAD macro for example



  * src_addr_widths:

    - should contain a bitmask of the supported source transfer width



  * dst_addr_widths:

    - should contain a bitmask of the supported destination transfer

      width



  * directions:

    - should contain a bitmask of the supported slave directions

      (i.e. excluding mem2mem transfers)



  * residue_granularity:

    - Granularity of the transfer residue reported to dma_set_residue.

    - This can be either:

      + Descriptor

        -> Your device doesn't support any kind of residue

           reporting. The framework will only know that a particular

           transaction descriptor is done.

      + Segment

        -> Your device is able to report which chunks have been

           transferred

      + Burst

        -> Your device is able to report which burst have been

           transferred



  * dev: 	should hold the pointer to the struct device associated

		to your current driver instance.
@@ -274,48 +299,36 @@ supported. 
       account the current period.

     - This function can be called in an interrupt context.



   * device_control

     - Used by client drivers to control and configure the channel it

       has a handle on.

     - Called with a command and an argument

       + The command is one of the values listed by the enum

         dma_ctrl_cmd. The valid commands are:

         + DMA_PAUSE

           + Pauses a transfer on the channel

           + This command should operate synchronously on the channel,

   * device_config

     - Reconfigures the channel with the configuration given as

       argument

     - This command should NOT perform synchronously, or on any

       currently queued transfers, but only on subsequent ones

     - In this case, the function will receive a dma_slave_config

       structure pointer as an argument, that will detail which

       configuration to use.

     - Even though that structure contains a direction field, this

       field is deprecated in favor of the direction argument given to

       the prep_* functions

     - This call is mandatory for slave operations only. This should NOT be

       set or expected to be set for memcpy operations.

       If a driver support both, it should use this call for slave

       operations only and not for memcpy ones.



   * device_pause

     - Pauses a transfer on the channel

     - This command should operate synchronously on the channel,

       pausing right away the work of the given channel



   * device_resume

     - Resumes a transfer on the channel

     - This command should operate synchronously on the channel,

       pausing right away the work of the given channel

         + DMA_RESUME

           + Restarts a transfer on the channel

           + This command should operate synchronously on the channel,

             resuming right away the work of the given channel

         + DMA_TERMINATE_ALL

           + Aborts all the pending and ongoing transfers on the

             channel

           + This command should operate synchronously on the channel,



   * device_terminate_all

     - Aborts all the pending and ongoing transfers on the channel

     - This command should operate synchronously on the channel,

       terminating right away all the channels

         + DMA_SLAVE_CONFIG

           + Reconfigures the channel with passed configuration

           + This command should NOT perform synchronously, or on any

             currently queued transfers, but only on subsequent ones

           + In this case, the function will receive a

             dma_slave_config structure pointer as an argument, that

             will detail which configuration to use.

           + Even though that structure contains a direction field,

             this field is deprecated in favor of the direction

             argument given to the prep_* functions

         + FSLDMA_EXTERNAL_START

           + TODO: Why does that even exist?

       + The argument is an opaque unsigned long. This actually is a

         pointer to a struct dma_slave_config that should be used only

         in the DMA_SLAVE_CONFIG.



  * device_slave_caps

    - Called through the framework by client drivers in order to have

      an idea of what are the properties of the channel allocated to

      them.

    - Such properties are the buswidth, available directions, etc.

    - Required for every generic layer doing DMA transfers, such as

      ASoC.



Misc notes (stuff that should be documented, but don't really know

where to put them)

MAINTAINERS

+1 −0
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@@ -8503,6 +8503,7 @@ SYNOPSYS DESIGNWARE DMAC DRIVER 
M:	Viresh Kumar <viresh.linux@gmail.com>

M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

S:	Maintained

F:	include/linux/dma/dw.h

F:	include/linux/platform_data/dma-dw.h

F:	drivers/dma/dw/