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Commit cdfc8307 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "The most notable new addition inside this pull request is the support
  for MIPS's latest and greatest core called "inter/proAptiv".  The
  patch series describes this core as follows.

    "The interAptiv is a power-efficient multi-core microprocessor
     for use in system-on-chip (SoC) applications. The interAptiv combines
     a multi-threading pipeline with a coherence manager to deliver improved
     computational throughput and power efficiency. The interAptiv can
     contain one to four MIPS32R3 interAptiv cores, system level
     coherence manager with L2 cache, optional coherent I/O port,
     and optional floating point unit."

  The platform specific patches touch all 3 Broadcom families.  It adds
  support for the new Broadcom/Netlogix XLP9xx Soc, building a common
  BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
  and full gpio button/led descriptions for BCM47xx.

  The rest of the series are cleanups and bug fixes that are MIPS
  generic and consist largely of changes that Imgtec/MIPS had published
  in their linux-mti-3.10.git stable tree.  Random other cleanups and
  patches preparing code to be merged in 3.15"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  mips: select ARCH_MIGHT_HAVE_PC_SERIO
  mips: delete non-required instances of include <linux/init.h>
  MIPS: KVM: remove shadow_tlb code
  MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
  mips/ide: flush dcache also if icache does not snoop dcache
  MIPS: BCM47XX: fix position of cpu_wait disabling
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: ZBOOT: gather string functions into string.c
  arch/mips/pci: don't check resource with devm_ioremap_resource
  arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
  bcma: gpio: don't cast u32 to unsigned long
  ssb: gpio: add own IRQ domain
  MIPS: BCM47XX: fix sparse warnings in board.c
  MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
  MIPS: BCM47XX: fix detection for some boards
  MIPS: BCM47XX: Enable buttons support on SSB
  MIPS: BCM47XX: Convert WNDR4500 to new syntax
  MIPS: BCM47XX: Use "timer" trigger for status LEDs
  ...
parents 04a24ae4 b26a21c1

arch/mips/Kconfig

+133 −88
Original line number Diff line number Diff line
@@ -116,7 +116,6 @@ config BCM47XX 
	select CEVT_R4K

	select CSRC_R4K

	select DMA_NONCOHERENT

	select FW_CFE

	select HW_HAS_PCI

	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1
@@ -124,6 +123,7 @@ config BCM47XX 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_HAS_EARLY_PRINTK

	select EARLY_PRINTK_8250 if EARLY_PRINTK

	help

	 Support for BCM47XX based boards
@@ -134,14 +134,13 @@ config BCM63XX 
	select CSRC_R4K

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_HAS_EARLY_PRINTK

	select SWAP_IO_SPACE

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select MIPS_L1_CACHE_SHIFT_4

	help

	 Support for BCM63XX based boards
@@ -186,6 +185,7 @@ config MACH_DECSTATION 
	select SYS_SUPPORTS_128HZ

	select SYS_SUPPORTS_256HZ

	select SYS_SUPPORTS_1024HZ

	select MIPS_L1_CACHE_SHIFT_4

	help

	  This enables support for DEC's MIPS based workstations.  For details

	  see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -305,7 +305,7 @@ config MIPS_MALTA 
	select CEVT_R4K

	select CSRC_R4K

	select CSRC_GIC

	select DMA_NONCOHERENT

	select DMA_MAYBE_COHERENT

	select GENERIC_ISA_DMA

	select HAVE_PCSPKR_PLATFORM

	select IRQ_CPU
@@ -324,7 +324,6 @@ config MIPS_MALTA 
	select SYS_HAS_CPU_MIPS64_R2

	select SYS_HAS_CPU_NEVADA

	select SYS_HAS_CPU_RM7000

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN
@@ -349,6 +348,7 @@ config MIPS_SEAD3 
	select DMA_NONCOHERENT

	select IRQ_CPU

	select IRQ_GIC

	select LIBFDT

	select MIPS_MSC

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2
@@ -471,6 +471,7 @@ config SGI_IP22 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain

	  OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -491,6 +492,7 @@ config SGI_IP27 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_NUMA

	select SYS_SUPPORTS_SMP

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics

	  workstations.  To compile a Linux kernel that runs on these, say Y
@@ -697,6 +699,7 @@ config MIKROTIK_RB532 
	select SWAP_IO_SPACE

	select BOOT_RAW

	select ARCH_REQUIRE_GPIOLIB

	select MIPS_L1_CACHE_SHIFT_4

	help

	  Support the Mikrotik(tm) RouterBoard 532 series,

	  based on the IDT RC32434 SoC.
@@ -779,6 +782,7 @@ config NLM_XLP_BOARD 
	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU

	select ARCH_SUPPORTS_MSI

	select ZONE_DMA32 if 64BIT

	select SYNC_R4K

	select SYS_HAS_EARLY_PRINTK
@@ -897,6 +901,10 @@ config FW_CFE 
config ARCH_DMA_ADDR_T_64BIT

	def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT



config DMA_MAYBE_COHERENT

	select DMA_NONCOHERENT

	bool



config DMA_COHERENT

	bool
@@ -1091,11 +1099,24 @@ config FW_SNIPROM 
config BOOT_ELF32

	bool



config MIPS_L1_CACHE_SHIFT_4

	bool



config MIPS_L1_CACHE_SHIFT_5

	bool



config MIPS_L1_CACHE_SHIFT_6

	bool



config MIPS_L1_CACHE_SHIFT_7

	bool



config MIPS_L1_CACHE_SHIFT

	int

	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X

	default "6" if MIPS_CPU_SCACHE

	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

	default "4" if MIPS_L1_CACHE_SHIFT_4

	default "5" if MIPS_L1_CACHE_SHIFT_5

	default "6" if MIPS_L1_CACHE_SHIFT_6

	default "7" if MIPS_L1_CACHE_SHIFT_7

	default "5"



config HAVE_STD_PC_SERIAL_PORT
@@ -1375,47 +1396,31 @@ config CPU_CAVIUM_OCTEON 
	select LIBFDT

	select USE_OF

	select USB_EHCI_BIG_ENDIAN_MMIO

	select SYS_HAS_DMA_OPS

	select MIPS_L1_CACHE_SHIFT_7

	help

	  The Cavium Octeon processor is a highly integrated chip containing

	  many ethernet hardware widgets for networking tasks. The processor

	  can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.

	  Full details can be found at http://www.caviumnetworks.com.



config CPU_BMIPS3300

	bool "BMIPS3300"

	depends on SYS_HAS_CPU_BMIPS3300

	select CPU_BMIPS

	help

	  Broadcom BMIPS3300 processors.



config CPU_BMIPS4350

	bool "BMIPS4350"

	depends on SYS_HAS_CPU_BMIPS4350

	select CPU_BMIPS

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	help

	  Broadcom BMIPS4350 ("VIPER") processors.



config CPU_BMIPS4380

	bool "BMIPS4380"

	depends on SYS_HAS_CPU_BMIPS4380

	select CPU_BMIPS

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	help

	  Broadcom BMIPS4380 processors.



config CPU_BMIPS5000

	bool "BMIPS5000"

	depends on SYS_HAS_CPU_BMIPS5000

	select CPU_BMIPS

config CPU_BMIPS

	bool "Broadcom BMIPS"

	depends on SYS_HAS_CPU_BMIPS

	select CPU_MIPS32

	select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300

	select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350

	select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380

	select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000

	select CPU_SUPPORTS_32BIT_KERNEL

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select WEAK_ORDERING

	select CPU_SUPPORTS_HIGHMEM

	select MIPS_CPU_SCACHE

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	select CPU_HAS_PREFETCH

	help

	  Broadcom BMIPS5000 processors.

	  Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.



config CPU_XLR

	bool "Netlogic XLR SoC"
@@ -1498,14 +1503,25 @@ config CPU_LOONGSON1 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM



config CPU_BMIPS

config CPU_BMIPS32_3300

	select SMP_UP if SMP

	bool

	select CPU_MIPS32

	select CPU_SUPPORTS_32BIT_KERNEL

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select WEAK_ORDERING



config CPU_BMIPS4350

	bool

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU



config CPU_BMIPS4380

	bool

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU



config CPU_BMIPS5000

	bool

	select MIPS_CPU_SCACHE

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU



config SYS_HAS_CPU_LOONGSON2E

	bool
@@ -1579,17 +1595,24 @@ config SYS_HAS_CPU_SB1 
config SYS_HAS_CPU_CAVIUM_OCTEON

	bool



config SYS_HAS_CPU_BMIPS3300

config SYS_HAS_CPU_BMIPS

	bool



config SYS_HAS_CPU_BMIPS32_3300

	bool

	select SYS_HAS_CPU_BMIPS



config SYS_HAS_CPU_BMIPS4350

	bool

	select SYS_HAS_CPU_BMIPS



config SYS_HAS_CPU_BMIPS4380

	bool

	select SYS_HAS_CPU_BMIPS



config SYS_HAS_CPU_BMIPS5000

	bool

	select SYS_HAS_CPU_BMIPS



config SYS_HAS_CPU_XLR

	bool
@@ -1797,6 +1820,7 @@ config IP22_CPU_SCACHE 
config MIPS_CPU_SCACHE

	bool

	select BOARD_SCACHE

	select MIPS_L1_CACHE_SHIFT_6



config R5000_CPU_SCACHE

	bool
@@ -1833,59 +1857,48 @@ choice 
	prompt "MIPS MT options"



config MIPS_MT_DISABLED

	bool "Disable multithreading support."

	bool "Disable multithreading support"

	help

	  Use this option if your workload can't take advantage of

	  MIPS hardware multithreading support.  On systems that don't have

	  the option of an MT-enabled processor this option will be the only

	  option in this menu.

	  Use this option if your platform does not support the MT ASE

	  which is hardware multithreading support. On systems without

	  an MT-enabled processor, this will be the only option that is

	  available in this menu.



config MIPS_MT_SMP

	bool "Use 1 TC on each available VPE for SMP"

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select SYNC_R4K

	select MIPS_MT

	select SMP

	select SYS_SUPPORTS_SCHED_SMT if SMP

	select SYS_SUPPORTS_SMP

	select SMP_UP

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_SCHED_SMT

	select MIPS_PERF_SHARED_TC_COUNTERS

	help

	  This is a kernel model which is known a VSMP but lately has been

	  marketesed into SMVP.

	  Virtual SMP uses the processor's VPEs  to implement virtual

	  processors. In currently available configuration of the 34K processor

	  this allows for a dual processor. Both processors will share the same

	  primary caches; each will obtain the half of the TLB for it's own

	  exclusive use. For a layman this model can be described as similar to

	  what Intel calls Hyperthreading.



	  For further information see http://www.linux-mips.org/wiki/34K#VSMP

	  This is a kernel model which is known as SMVP. This is supported

	  on cores with the MT ASE and uses the available VPEs to implement

	  virtual processors which supports SMP. This is equivalent to the

	  Intel Hyperthreading feature. For further information go to

	  <http://www.imgtec.com/mips/mips-multithreading.asp>.



config MIPS_MT_SMTC

	bool "SMTC: Use all TCs on all VPEs for SMP"

	bool "Use all TCs on all VPEs for SMP (DEPRECATED)"

	depends on CPU_MIPS32_R2

	#depends on CPU_MIPS64_R2		# once there is hardware ...

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select MIPS_MT

	select NR_CPUS_DEFAULT_8

	select SMP

	select SYS_SUPPORTS_SMP

	select SMP_UP

	select SYS_SUPPORTS_SMP

	select NR_CPUS_DEFAULT_8

	help

	  This is a kernel model which is known a SMTC or lately has been

	  marketesed into SMVP.

	  is presenting the available TC's of the core as processors to Linux.

	  On currently available 34K processors this means a Linux system will

	  see up to 5 processors. The implementation of the SMTC kernel differs

	  significantly from VSMP and cannot efficiently coexist in the same

	  kernel binary so the choice between VSMP and SMTC is a compile time

	  decision.



	  For further information see http://www.linux-mips.org/wiki/34K#SMTC

	  This is a kernel model which is known as SMTC. This is

	  supported on cores with the MT ASE and presents all TCs

	  available on all VPEs to support SMP. For further

	  information see <http://www.linux-mips.org/wiki/34K#SMTC>.



endchoice
@@ -1922,6 +1935,16 @@ config MIPS_VPE_LOADER 
	  Includes a loader for loading an elf relocatable object

	  onto another VPE and running it.



config MIPS_VPE_LOADER_CMP

	bool

	default "y"

	depends on MIPS_VPE_LOADER && MIPS_CMP



config MIPS_VPE_LOADER_MT

	bool

	default "y"

	depends on MIPS_VPE_LOADER && !MIPS_CMP



config MIPS_MT_SMTC_IM_BACKSTOP

	bool "Use per-TC register bits as backstop for inhibited IM bits"

	depends on MIPS_MT_SMTC
@@ -1955,24 +1978,29 @@ config MIPS_VPE_LOADER_TOM 
	  you to ensure the amount you put in the option and the space your

	  program requires is less or equal to the amount physically present.



# this should possibly be in drivers/char, but it is rather cpu related. Hmmm

config MIPS_VPE_APSP_API

	bool "Enable support for AP/SP API (RTLX)"

	depends on MIPS_VPE_LOADER

	help



config MIPS_VPE_APSP_API_CMP

	bool

	default "y"

	depends on MIPS_VPE_APSP_API && MIPS_CMP



config MIPS_VPE_APSP_API_MT

	bool

	default "y"

	depends on MIPS_VPE_APSP_API && !MIPS_CMP



config MIPS_CMP

	bool "MIPS CMP framework support"

	depends on SYS_SUPPORTS_MIPS_CMP

	select SMP

	bool "MIPS CMP support"

	depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP

	select SYNC_R4K

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_SCHED_SMT if SMP

	select WEAK_ORDERING

	default n

	help

	  This is a placeholder option for the GCMP work. It will need to

	  be handled differently...

	  Enable Coherency Manager processor (CMP) support.



config SB1_PASS_1_WORKAROUNDS

	bool
@@ -2324,6 +2352,23 @@ config SECCOMP 


	  If unsure, say Y. Only embedded should say N here.



config MIPS_O32_FP64_SUPPORT

	bool "Support for O32 binaries using 64-bit FP"

	depends on 32BIT || MIPS32_O32

	default y

	help

	  When this is enabled, the kernel will support use of 64-bit floating

	  point registers with binaries using the O32 ABI along with the

	  EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On

	  32-bit MIPS systems this support is at the cost of increasing the

	  size and complexity of the compiled FPU emulator. Thus if you are

	  running a MIPS32 system and know that none of your userland binaries

	  will require 64-bit floating point, you may wish to reduce the size

	  of your kernel & potentially improve FP emulation performance by

	  saying N here.



	  If unsure, say Y.



config USE_OF

	bool

	select OF

arch/mips/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e 
cflags-$(CONFIG_CPU_LITTLE_ENDIAN)	+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))



cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= $(call cc-option,-msmartmips)

cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals)

cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)



cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \

				   -fno-omit-frame-pointer

arch/mips/alchemy/common/power.c

+0 −1
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
 *  675 Mass Ave, Cambridge, MA 02139, USA.

 */



#include <linux/init.h>

#include <linux/pm.h>

#include <linux/sysctl.h>

#include <linux/jiffies.h>

arch/mips/ar7/time.c

+0 −1
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
 * Setting up the clock on the MIPS boards.

 */



#include <linux/init.h>

#include <linux/time.h>

#include <linux/err.h>

#include <linux/clk.h>

arch/mips/ath79/common.h

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 
#define __ATH79_COMMON_H



#include <linux/types.h>

#include <linux/init.h>



#define ATH79_MEM_SIZE_MIN	(2 * 1024 * 1024)

#define ATH79_MEM_SIZE_MAX	(128 * 1024 * 1024)