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Commit cda82ace authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Stephen Boyd
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dt-bindings: arm: update Armada CP110 system controller binding 



It turns out that in the CP110 HW block present in Marvell Armada
7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the
GOP block. This commit updates the Device Tree binding for this piece
of hardware accordingly.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent c1ae3cfa

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

+3 −3
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ The following clocks are available: 
   - 1 15	SATA

   - 1 16	SATA USB

   - 1 17	Main

   - 1 18	SD/MMC

   - 1 18	SD/MMC/GOP

   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)

   - 1 22	USB3H0

   - 1 23	USB3H1
@@ -65,7 +65,7 @@ Required properties: 
	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",

	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",

	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";



Example:
@@ -78,6 +78,6 @@ Example: 
		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",

			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",

			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",

			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",

			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",

			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

	};