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Commit cd6f5545 authored by Viresh Kumar's avatar Viresh Kumar Committed by Krzysztof Kozlowski
Browse files

ARM: dts: exynos: Remove "cooling-{min|max}-level" for CPU nodes 



The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.

Remove the unused properties from the CPU nodes.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent bd010d60

arch/arm/boot/dts/exynos4210.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -48,8 +48,6 @@ 
				400000	975000

				200000	950000

			>;

			cooling-min-level = <4>;

			cooling-max-level = <2>;

			#cooling-cells = <2>; /* min followed by max */

		};

arch/arm/boot/dts/exynos4412.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -42,8 +42,6 @@ 
			clocks = <&clock CLK_ARM_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			cooling-min-level = <13>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

		};

arch/arm/boot/dts/exynos5250.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -77,8 +77,6 @@ 
				 300000  937500

				 200000  925000

			>;

			cooling-min-level = <15>;

			cooling-max-level = <9>;

			#cooling-cells = <2>; /* min followed by max */

		};

		cpu@1 {

arch/arm/boot/dts/exynos5420-cpus.dtsi

+0 −16
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -43,8 +41,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -56,8 +52,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -69,8 +63,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -83,8 +75,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -96,8 +86,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -109,8 +97,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -122,8 +108,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};

arch/arm/boot/dts/exynos5422-cpus.dtsi

+0 −16
Original line number Diff line number Diff line
@@ -29,8 +29,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -42,8 +40,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -55,8 +51,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -68,8 +62,6 @@ 
			clock-frequency = <1000000000>;

			cci-control-port = <&cci_control0>;

			operating-points-v2 = <&cluster_a7_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <11>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <539>;

		};
@@ -82,8 +74,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <15>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -95,8 +85,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <15>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -108,8 +96,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <15>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};
@@ -121,8 +107,6 @@ 
			clock-frequency = <1800000000>;

			cci-control-port = <&cci_control1>;

			operating-points-v2 = <&cluster_a15_opp_table>;

			cooling-min-level = <0>;

			cooling-max-level = <15>;

			#cooling-cells = <2>; /* min followed by max */

			capacity-dmips-mhz = <1024>;

		};