ath9k: do not set half/quarter channel flags in AR_PHY_MODE

5/10 MHz channel bandwidth is configured via the PLL clock, instead of
the AR_PHY_MODE register. Using that register is AR93xx specific, and
makes the mode incompatible with earlier chipsets.

In some early versions, these flags were apparently applied at the wrong
point in time and thus did not cause connectivity issues, however now
they are causing problems, as pointed out in this OpenWrt ticket:

https://dev.openwrt.org/ticket/14916



Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>