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Commit cd407abd authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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coresight tmc etr: Cleanup AXICTL register handling 



This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ff11f5bc

drivers/hwtracing/coresight/coresight-tmc-etr.c

+3 −7
Original line number Original line Diff line number Diff line
@@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) 
	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);

	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);





	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);

	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);

	axictl |= TMC_AXICTL_WR_BURST_16;

	axictl &= ~TMC_AXICTL_CLEAR_MASK;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);

	axictl &= ~TMC_AXICTL_SCT_GAT_MODE;

	axictl |= TMC_AXICTL_AXCACHE_OS;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	axictl = (axictl &

		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |

		  TMC_AXICTL_PROT_CTL_B1;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	tmc_write_dba(drvdata, drvdata->paddr);

	tmc_write_dba(drvdata, drvdata->paddr);

drivers/hwtracing/coresight/coresight-tmc.h

+16 −1
Original line number Original line Diff line number Diff line
@@ -54,11 +54,26 @@ 
#define TMC_STS_TMCREADY_BIT	2

#define TMC_STS_TMCREADY_BIT	2

#define TMC_STS_FULL		BIT(0)

#define TMC_STS_FULL		BIT(0)

#define TMC_STS_TRIGGERED	BIT(1)

#define TMC_STS_TRIGGERED	BIT(1)

/* TMC_AXICTL - 0x110 */

/*

 * TMC_AXICTL - 0x110

 *

 * TMC AXICTL format for SoC-400

 *	Bits [0-1]	: ProtCtrlBit0-1

 *	Bits [2-5]	: CacheCtrlBits 0-3 (AxCACHE)

 *	Bit  6		: Reserved

 *	Bit  7		: ScatterGatherMode

 *	Bits [8-11]	: WrBurstLen

 *	Bits [12-31]	: Reserved.

 */

#define TMC_AXICTL_CLEAR_MASK 0xfbf



#define TMC_AXICTL_PROT_CTL_B0	BIT(0)

#define TMC_AXICTL_PROT_CTL_B0	BIT(0)

#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_WR_BURST_16	0xF00

#define TMC_AXICTL_WR_BURST_16	0xF00

/* Write-back Read and Write-allocate */

#define TMC_AXICTL_AXCACHE_OS	(0xf << 2)



/* TMC_FFCR - 0x304 */

/* TMC_FFCR - 0x304 */

#define TMC_FFCR_FLUSHMAN_BIT	6

#define TMC_FFCR_FLUSHMAN_BIT	6

#define TMC_FFCR_EN_FMT		BIT(0)

#define TMC_FFCR_EN_FMT		BIT(0)