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Commit cd32cc73 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: punt OTP MMRs 



People should not be accessing OTP MMRs directly.  They should instead go
through the Blackfin ROM helper functions.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent b1fa2e8f

arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h

+0 −22
Original line number Diff line number Diff line
@@ -1046,17 +1046,6 @@ 
#define bfin_read_CNT_MIN()			bfin_read32(CNT_MIN)

#define bfin_write_CNT_MIN(val)			bfin_write32(CNT_MIN, val)



/* OTP/FUSE Registers */



#define bfin_read_OTP_CONTROL()			bfin_read16(OTP_CONTROL)

#define bfin_write_OTP_CONTROL(val)		bfin_write16(OTP_CONTROL, val)

#define bfin_read_OTP_BEN()			bfin_read16(OTP_BEN)

#define bfin_write_OTP_BEN(val)			bfin_write16(OTP_BEN, val)

#define bfin_read_OTP_STATUS()			bfin_read16(OTP_STATUS)

#define bfin_write_OTP_STATUS(val)		bfin_write16(OTP_STATUS, val)

#define bfin_read_OTP_TIMING()			bfin_read32(OTP_TIMING)

#define bfin_write_OTP_TIMING(val)		bfin_write32(OTP_TIMING, val)



/* Security Registers */



#define bfin_read_SECURE_SYSSWT()		bfin_read32(SECURE_SYSSWT)
@@ -1066,17 +1055,6 @@ 
#define bfin_read_SECURE_STATUS()		bfin_read16(SECURE_STATUS)

#define bfin_write_SECURE_STATUS(val)		bfin_write16(SECURE_STATUS, val)



/* OTP Read/Write Data Buffer Registers */



#define bfin_read_OTP_DATA0()			bfin_read32(OTP_DATA0)

#define bfin_write_OTP_DATA0(val)		bfin_write32(OTP_DATA0, val)

#define bfin_read_OTP_DATA1()			bfin_read32(OTP_DATA1)

#define bfin_write_OTP_DATA1(val)		bfin_write32(OTP_DATA1, val)

#define bfin_read_OTP_DATA2()			bfin_read32(OTP_DATA2)

#define bfin_write_OTP_DATA2(val)		bfin_write32(OTP_DATA2, val)

#define bfin_read_OTP_DATA3()			bfin_read32(OTP_DATA3)

#define bfin_write_OTP_DATA3(val)		bfin_write32(OTP_DATA3, val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/irq.h>

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+0 −40
Original line number Diff line number Diff line
@@ -1770,46 +1770,6 @@ 
#define BNDMODE_CAPT     0x2000  /* boundary capture mode */

#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */



/* Bit masks for OTP_CONTROL */



#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */

#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */

#define                     nFIEN  0x0

#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */

#define                 nFTESTDEC  0x0

#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */

#define                  nFWRTEST  0x0

#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */

#define                    nFRDEN  0x0

#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */

#define                    nFWREN  0x0



/* Bit masks for OTP_BEN */



#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */



/* Bit masks for OTP_STATUS */



#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */

#define                    nFCOMP  0x0

#define                    FERROR  0x2        /* OTP/Fuse Access Error */

#define                   nFERROR  0x0

#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */

#define                 nMMRGLOAD  0x0

#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */

#define                 nMMRGLOCK  0x0

#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */

#define                   nFPGMEN  0x0



/* Bit masks for OTP_TIMING */



#define                   USECDIV  0xff       /* Micro Second Divider */

#define                   READACC  0x7f00     /* Read Access Time */

#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */

#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */

#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */

#define                   PGMTIME  0xff000000 /* Program Time */



/* Bit masks for SECURE_SYSSWT */



#define                   EMUDABL  0x1        /* Emulation Disable. */

arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h

+0 −22
Original line number Diff line number Diff line
@@ -1063,17 +1063,6 @@ 
#define bfin_read_CNT_MIN()			bfin_read32(CNT_MIN)

#define bfin_write_CNT_MIN(val)			bfin_write32(CNT_MIN, val)



/* OTP/FUSE Registers */



#define bfin_read_OTP_CONTROL()			bfin_read16(OTP_CONTROL)

#define bfin_write_OTP_CONTROL(val)		bfin_write16(OTP_CONTROL, val)

#define bfin_read_OTP_BEN()			bfin_read16(OTP_BEN)

#define bfin_write_OTP_BEN(val)			bfin_write16(OTP_BEN, val)

#define bfin_read_OTP_STATUS()			bfin_read16(OTP_STATUS)

#define bfin_write_OTP_STATUS(val)		bfin_write16(OTP_STATUS, val)

#define bfin_read_OTP_TIMING()			bfin_read32(OTP_TIMING)

#define bfin_write_OTP_TIMING(val)		bfin_write32(OTP_TIMING, val)



/* Security Registers */



#define bfin_read_SECURE_SYSSWT()		bfin_read32(SECURE_SYSSWT)
@@ -1083,17 +1072,6 @@ 
#define bfin_read_SECURE_STATUS()		bfin_read16(SECURE_STATUS)

#define bfin_write_SECURE_STATUS(val)		bfin_write16(SECURE_STATUS, val)



/* OTP Read/Write Data Buffer Registers */



#define bfin_read_OTP_DATA0()			bfin_read32(OTP_DATA0)

#define bfin_write_OTP_DATA0(val)		bfin_write32(OTP_DATA0, val)

#define bfin_read_OTP_DATA1()			bfin_read32(OTP_DATA1)

#define bfin_write_OTP_DATA1(val)		bfin_write32(OTP_DATA1, val)

#define bfin_read_OTP_DATA2()			bfin_read32(OTP_DATA2)

#define bfin_write_OTP_DATA2(val)		bfin_write32(OTP_DATA2, val)

#define bfin_read_OTP_DATA3()			bfin_read32(OTP_DATA3)

#define bfin_write_OTP_DATA3(val)		bfin_write32(OTP_DATA3, val)



/* NFC Registers */



#define bfin_read_NFC_CTL()			bfin_read16(NFC_CTL)

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

+0 −40
Original line number Diff line number Diff line
@@ -1783,46 +1783,6 @@ 
#define BNDMODE_CAPT     0x2000  /* boundary capture mode */

#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */



/* Bit masks for OTP_CONTROL */



#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */

#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */

#define                     nFIEN  0x0

#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */

#define                 nFTESTDEC  0x0

#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */

#define                  nFWRTEST  0x0

#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */

#define                    nFRDEN  0x0

#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */

#define                    nFWREN  0x0



/* Bit masks for OTP_BEN */



#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */



/* Bit masks for OTP_STATUS */



#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */

#define                    nFCOMP  0x0

#define                    FERROR  0x2        /* OTP/Fuse Access Error */

#define                   nFERROR  0x0

#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */

#define                 nMMRGLOAD  0x0

#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */

#define                 nMMRGLOCK  0x0

#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */

#define                   nFPGMEN  0x0



/* Bit masks for OTP_TIMING */



#define                   USECDIV  0xff       /* Micro Second Divider */

#define                   READACC  0x7f00     /* Read Access Time */

#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */

#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */

#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */

#define                   PGMTIME  0xff000000 /* Program Time */



/* Bit masks for SECURE_SYSSWT */



#define                   EMUDABL  0x1        /* Emulation Disable. */

arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h

+0 −22
Original line number Diff line number Diff line
@@ -2615,17 +2615,6 @@ 
#define bfin_read_CNT_MIN()		bfin_read32(CNT_MIN)

#define bfin_write_CNT_MIN(val)		bfin_write32(CNT_MIN, val)



/* OTP/FUSE Registers */



#define bfin_read_OTP_CONTROL()		bfin_read16(OTP_CONTROL)

#define bfin_write_OTP_CONTROL(val)	bfin_write16(OTP_CONTROL, val)

#define bfin_read_OTP_BEN()		bfin_read16(OTP_BEN)

#define bfin_write_OTP_BEN(val)		bfin_write16(OTP_BEN, val)

#define bfin_read_OTP_STATUS()		bfin_read16(OTP_STATUS)

#define bfin_write_OTP_STATUS(val)	bfin_write16(OTP_STATUS, val)

#define bfin_read_OTP_TIMING()		bfin_read32(OTP_TIMING)

#define bfin_write_OTP_TIMING(val)	bfin_write32(OTP_TIMING, val)



/* Security Registers */



#define bfin_read_SECURE_SYSSWT()	bfin_read32(SECURE_SYSSWT)
@@ -2640,17 +2629,6 @@ 
#define bfin_read_DMAC1_PERIMUX()	bfin_read16(DMAC1_PERIMUX)

#define bfin_write_DMAC1_PERIMUX(val)	bfin_write16(DMAC1_PERIMUX, val)



/* OTP Read/Write Data Buffer Registers */



#define bfin_read_OTP_DATA0()		bfin_read32(OTP_DATA0)

#define bfin_write_OTP_DATA0(val)	bfin_write32(OTP_DATA0, val)

#define bfin_read_OTP_DATA1()		bfin_read32(OTP_DATA1)

#define bfin_write_OTP_DATA1(val)	bfin_write32(OTP_DATA1, val)

#define bfin_read_OTP_DATA2()		bfin_read32(OTP_DATA2)

#define bfin_write_OTP_DATA2(val)	bfin_write32(OTP_DATA2, val)

#define bfin_read_OTP_DATA3()		bfin_read32(OTP_DATA3)

#define bfin_write_OTP_DATA3(val)	bfin_write32(OTP_DATA3, val)



/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */



/* legacy definitions */