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Commit cd06bf68 authored by Ben Goz's avatar Ben Goz Committed by Alex Deucher
Browse files

drm/amdgpu: Initialize compute sdma and memory from kgd 



v2: add missing MTYPE_NONCACHED enum

Signed-off-by: default avatarBen Goz <ben.goz@amd.com>
Acked-by: default avatarOded Gabbay <oded.gabbay@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 69ee2410

drivers/gpu/drm/amd/amdgpu/cikd.h

+6 −0
Original line number Diff line number Diff line
@@ -552,4 +552,10 @@ 
#define VCE_CMD_IB_AUTO		0x00000005

#define VCE_CMD_SEMAPHORE	0x00000006



/* valid for both DEFAULT_MTYPE and APE1_MTYPE */

enum {

	MTYPE_CACHED = 0,

	MTYPE_NONCACHED = 3

};



#endif

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+42 −0
Original line number Diff line number Diff line
@@ -2009,6 +2009,46 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev, 
	mutex_unlock(&adev->grbm_idx_mutex);

}



/**

 * gmc_v7_0_init_compute_vmid - gart enable

 *

 * @rdev: amdgpu_device pointer

 *

 * Initialize compute vmid sh_mem registers

 *

 */

#define DEFAULT_SH_MEM_BASES	(0x6000)

#define FIRST_COMPUTE_VMID	(8)

#define LAST_COMPUTE_VMID	(16)

static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)

{

	int i;

	uint32_t sh_mem_config;

	uint32_t sh_mem_bases;



	/*

	 * Configure apertures:

	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)

	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)

	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)

	*/

	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);

	sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<

			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;

	sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;

	mutex_lock(&adev->srbm_mutex);

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

		cik_srbm_select(adev, 0, 0, 0, i);

		/* CP and shaders */

		WREG32(mmSH_MEM_CONFIG, sh_mem_config);

		WREG32(mmSH_MEM_APE1_BASE, 1);

		WREG32(mmSH_MEM_APE1_LIMIT, 0);

		WREG32(mmSH_MEM_BASES, sh_mem_bases);

	}

	cik_srbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);

}



/**

 * gfx_v7_0_gpu_init - setup the 3D engine

 *
@@ -2230,6 +2270,8 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 
	cik_srbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	gmc_v7_0_init_compute_vmid(adev);



	WREG32(mmSX_DEBUG_1, 0x20);



	WREG32(mmTA_CNTL_AUX, 0x00010000);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+47 −0
Original line number Diff line number Diff line
@@ -1894,6 +1894,51 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, 
	mutex_unlock(&adev->grbm_idx_mutex);

}



/**

 * gmc_v8_0_init_compute_vmid - gart enable

 *

 * @rdev: amdgpu_device pointer

 *

 * Initialize compute vmid sh_mem registers

 *

 */

#define DEFAULT_SH_MEM_BASES	(0x6000)

#define FIRST_COMPUTE_VMID	(8)

#define LAST_COMPUTE_VMID	(16)

static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)

{

	int i;

	uint32_t sh_mem_config;

	uint32_t sh_mem_bases;



	/*

	 * Configure apertures:

	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)

	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)

	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)

	 */

	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);



	sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<

			SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |

			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<

			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |

			MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |

			SH_MEM_CONFIG__PRIVATE_ATC_MASK;



	mutex_lock(&adev->srbm_mutex);

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

		vi_srbm_select(adev, 0, 0, 0, i);

		/* CP and shaders */

		WREG32(mmSH_MEM_CONFIG, sh_mem_config);

		WREG32(mmSH_MEM_APE1_BASE, 1);

		WREG32(mmSH_MEM_APE1_LIMIT, 0);

		WREG32(mmSH_MEM_BASES, sh_mem_bases);

	}

	vi_srbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);

}



static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)

{

	u32 gb_addr_config;
@@ -2113,6 +2158,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
	vi_srbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	gmc_v8_0_init_compute_vmid(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	/*

	 * making sure that the following register writes will be broadcasted

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+28 −0
Original line number Diff line number Diff line
@@ -438,6 +438,31 @@ static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 
	/* XXX todo */

}



/**

 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch

 *

 * @adev: amdgpu_device pointer

 * @enable: enable/disable the DMA MEs context switch.

 *

 * Halt or unhalt the async dma engines context switch (VI).

 */

static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)

{

	u32 f32_cntl;

	int i;



	for (i = 0; i < SDMA_MAX_INSTANCE; i++) {

		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);

		if (enable)

			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

					AUTO_CTXSW_ENABLE, 1);

		else

			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

					AUTO_CTXSW_ENABLE, 0);

		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);

	}

}



/**

 * sdma_v3_0_enable - stop the async dma engines

 *
@@ -648,6 +673,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) 


	/* unhalt the MEs */

	sdma_v3_0_enable(adev, true);

	/* enable sdma ring preemption */

	sdma_v3_0_ctx_switch_enable(adev, true);



	/* start the gfx rings and rlc compute queues */

	r = sdma_v3_0_gfx_resume(adev);
@@ -1079,6 +1106,7 @@ static int sdma_v3_0_hw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	sdma_v3_0_ctx_switch_enable(adev, false);

	sdma_v3_0_enable(adev, false);



	return 0;