Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cc6c9848 authored by Palmer Dabbelt's avatar Palmer Dabbelt Committed by Thomas Gleixner
Browse files

RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 



The existing mechanism for handling IRQs on RISC-V is pretty ugly: the irq
entry code selects the handler via Kconfig dependencies.

Use the new generic IRQ handling infastructure, which allows boot time
registration of the low level entry handler.

This does add an additional load to the interrupt latency, but there's a
lot of tuning left to be done there on RISC-V so it's OK for now.

Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarStafford Horne <shorne@gmail.com>
Cc: jonas@southpole.se
Cc: catalin.marinas@arm.com
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux@armlinux.org.uk
Cc: stefan.kristiansson@saunalahti.fi
Cc: openrisc@lists.librecores.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20180307235731.22627-3-palmer@sifive.com
parent caacdbf4

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ config RISCV 
	select MODULES_USE_ELF_RELA if MODULES

	select THREAD_INFO_IN_TASK

	select RISCV_TIMER

	select GENERIC_IRQ_MULTI_HANDLER



config MMU

	def_bool y

arch/riscv/include/asm/Kbuild

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ generic-y += fcntl.h 
generic-y += futex.h

generic-y += hardirq.h

generic-y += hash.h

generic-y += handle_irq.h

generic-y += hw_irq.h

generic-y += ioctl.h

generic-y += ioctls.h

arch/riscv/kernel/entry.S

+3 −4
Original line number Diff line number Diff line
@@ -167,10 +167,9 @@ ENTRY(handle_exception) 
	bge s4, zero, 1f



	/* Handle interrupts */

	slli a0, s4, 1

	srli a0, a0, 1

	move a1, sp /* pt_regs */

	tail do_IRQ

	move a0, sp /* pt_regs */

	REG_L a1, handle_arch_irq

	jr a1

1:

	/* Exceptions run with interrupts enabled */

	csrs sstatus, SR_SIE

arch/riscv/kernel/irq.c

+0 −13
Original line number Diff line number Diff line
@@ -24,16 +24,3 @@ void __init init_IRQ(void) 
{

	irqchip_init();

}
 


asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)

{

#ifdef CONFIG_RISCV_INTC

	/*

	 * FIXME: We don't want a direct call to riscv_intc_irq here.  The plan

	 * is to put an IRQ domain here and let the interrupt controller

	 * register with that, but I poked around the arm64 code a bit and

	 * there might be a better way to do it (ie, something fully generic).

	 */

	riscv_intc_irq(cause, regs);

#endif

}