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Commit cbb2fe8e authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: add bypass mode for vce 2.0. 



fix issue after vce encode, the eclk stay high.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0174df4e

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

+19 −2
Original line number Diff line number Diff line
@@ -30,10 +30,10 @@ 
#include "amdgpu.h"

#include "amdgpu_vce.h"

#include "cikd.h"



#include "vce/vce_2_0_d.h"

#include "vce/vce_2_0_sh_mask.h"



#include "smu/smu_7_0_1_d.h"

#include "smu/smu_7_0_1_sh_mask.h"

#include "oss/oss_2_0_d.h"

#include "oss/oss_2_0_sh_mask.h"
@@ -539,11 +539,28 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev, 
	return 0;

}



static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);



	if (enable)

		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;

	else

		tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;



	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);

}





static int vce_v2_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{

	bool gate = false;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;





	vce_v2_0_set_bypass_mode(adev, enable);



	if (state == AMD_CG_STATE_GATE)

		gate = true;