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Commit cb9e59d7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2) 



When this flag is set, we program the hardware to execute the flip
during horizontal blank (i.e. for the next scanline) instead of during
vertical blank (i.e. for the next frame).

Ported from radeon commit:
drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC

v2: drop DAL change for upstream

Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a71dd897

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −1
Original line number Diff line number Diff line
@@ -727,6 +727,7 @@ struct amdgpu_flip_work { 
	unsigned			shared_count;

	struct fence			**shared;

	struct fence_cb			cb;

	bool				async;

};
@@ -2243,7 +2244,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))

#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))

#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))

#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))

#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))

#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))

#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))

#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+2 −1
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work) 
				 vblank->linedur_ns / 1000, stat, vpos, hpos);



	/* Do the flip (mmio) */

	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);

	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);



	/* Set the flip status */

	amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
@@ -197,6 +197,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 
	work->event = event;

	work->adev = adev;

	work->crtc_id = amdgpu_crtc->crtc_id;

	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;



	/* schedule unpin of the old buffer */

	old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+1 −1
Original line number Diff line number Diff line
@@ -283,7 +283,7 @@ struct amdgpu_display_funcs { 
	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);

	/* pageflipping */

	void (*page_flip)(struct amdgpu_device *adev,

			 int crtc_id, u64 crtc_base);

			  int crtc_id, u64 crtc_base, bool async);

	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,

					u32 *vbl, u32 *position);

	/* display topology setup */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+17 −8
Original line number Diff line number Diff line
@@ -284,10 +284,16 @@ static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 
 * surface base address.

 */

static void dce_v10_0_page_flip(struct amdgpu_device *adev,

			      int crtc_id, u64 crtc_base)

				int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	u32 tmp;



	/* flip at hsync for async, default is vsync */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	/* update the primary scanout address */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));
@@ -2211,6 +2217,14 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 


	dce_v10_0_vga_enable(crtc, false);



	/* Make sure surface address is updated at vertical blank rather than

	 * horizontal blank

	 */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);



	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(fb_location));

	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
@@ -2261,13 +2275,6 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 
	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

	       (viewport_w << 16) | viewport_h);



	/* pageflip setup */

	/* make sure flip is at vb rather than hb */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);



	/* set pageflip to happen only at start of vblank interval (front porch) */

	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
@@ -2992,6 +2999,8 @@ static int dce_v10_0_sw_init(void *handle) 


	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;



	adev->ddev->mode_config.async_page_flip = true;



	adev->ddev->mode_config.max_width = 16384;

	adev->ddev->mode_config.max_height = 16384;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+18 −8
Original line number Diff line number Diff line
@@ -302,10 +302,17 @@ static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 
 * surface base address.

 */

static void dce_v11_0_page_flip(struct amdgpu_device *adev,

			      int crtc_id, u64 crtc_base)

				int crtc_id, u64 crtc_base, bool async)

{

	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];

	u32 tmp;



	/* flip at hsync for async, default is vsync */

	/* use UPDATE_IMMEDIATE_EN instead for async? */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

	/* update the scanout addresses */

	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(crtc_base));
@@ -2185,6 +2192,14 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 


	dce_v11_0_vga_enable(crtc, false);



	/* Make sure surface address is updated at vertical blank rather than

	 * horizontal blank

	 */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);



	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

	       upper_32_bits(fb_location));

	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
@@ -2235,13 +2250,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 
	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

	       (viewport_w << 16) | viewport_h);



	/* pageflip setup */

	/* make sure flip is at vb rather than hb */

	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);

	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);



	/* set pageflip to happen only at start of vblank interval (front porch) */

	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
@@ -3042,6 +3050,8 @@ static int dce_v11_0_sw_init(void *handle) 


	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;



	adev->ddev->mode_config.async_page_flip = true;



	adev->ddev->mode_config.max_width = 16384;

	adev->ddev->mode_config.max_height = 16384;