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Commit cb0d93aa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-4.8-rc2' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "This contains a bunch of amdgpu fixes, and some i915 regression fixes.

  It also contains some fixes for an older regression with some EDID
  changes and some 6bpc panels.

  Then there are the lockdep, cirrus and rcar-du regression fixes from
  this window"

* tag 'drm-fixes-for-4.8-rc2' of git://people.freedesktop.org/~airlied/linux:
  drm/cirrus: Fix NULL pointer dereference when registering the fbdev
  drm/edid: Set 8 bpc color depth for displays with "DFP 1.x compliant TMDS".
  drm/i915/dp: Revert "drm/i915/dp: fall back to 18 bpp when sink capability is unknown"
  drm/edid: Add 6 bpc quirk for display AEO model 0.
  drm: Paper over locking inversion after registration rework
  drm: rcar-du: Link HDMI encoder with bridge
  drm/ttm: Wait for a BO to become idle before unbinding it from GTT
  drm/i915/fbdev: Check for the framebuffer before use
  drm/amdgpu: update golden setting of polaris10
  drm/amdgpu: update golden setting of stoney
  drm/amdgpu: update golden setting of polaris11
  drm/amdgpu: update golden setting of carrizo
  drm/amdgpu: update golden setting of iceland
  drm/amd/amdgpu: change pptable output format from ASCII to binary
  drm/amdgpu/ci: add mullins to default case for smc ucode
  drm/amdgpu/gmc7: add missing mullins case
  drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB
  drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL
parents a3d1ddd9 36e9d08b

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+2 −5
Original line number Diff line number Diff line
@@ -305,7 +305,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev, 
	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = ddev->dev_private;

	char *table = NULL;

	int size, i;

	int size;



	if (adev->pp_enabled)

		size = amdgpu_dpm_get_pp_table(adev, &table);
@@ -315,10 +315,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev, 
	if (size >= PAGE_SIZE)

		size = PAGE_SIZE - 1;



	for (i = 0; i < size; i++) {

		sprintf(buf + i, "%02x", table[i]);

	}

	sprintf(buf + i, "\n");

	memcpy(buf, table, size);



	return size;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+2 −2
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 
	if (unlikely(r)) {

		goto out_cleanup;

	}

	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);

	r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, new_mem);

out_cleanup:

	ttm_bo_mem_put(bo, &tmp_mem);

	return r;
@@ -368,7 +368,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 
	if (unlikely(r)) {

		return r;

	}

	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);

	r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, &tmp_mem);

	if (unlikely(r)) {

		goto out_cleanup;

	}

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+1 −0
Original line number Diff line number Diff line
@@ -5779,6 +5779,7 @@ static int ci_dpm_init_microcode(struct amdgpu_device *adev) 
		break;

	case CHIP_KAVERI:

	case CHIP_KABINI:

	case CHIP_MULLINS:

	default: BUG();

	}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+8 −4
Original line number Diff line number Diff line
@@ -270,7 +270,8 @@ static const u32 tonga_mgcg_cgcg_init[] = 


static const u32 golden_settings_polaris11_a11[] =

{

	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,

	mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,

	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,

	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,

	mmDB_DEBUG2, 0xf00fffff, 0x00000400,

	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@@ -279,7 +280,7 @@ static const u32 golden_settings_polaris11_a11[] = 
	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,

	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,

	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,

	mmSQ_CONFIG, 0x07f80000, 0x07180000,

	mmSQ_CONFIG, 0x07f80000, 0x01180000,

	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,

	mmTCC_CTRL, 0x00100000, 0xf31fff7f,

	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
@@ -301,8 +302,8 @@ static const u32 polaris11_golden_common_all[] = 
static const u32 golden_settings_polaris10_a11[] =

{

	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,

	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,

	mmCB_HW_CONTROL_2, 0, 0x0f000000,

	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,

	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,

	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,

	mmDB_DEBUG2, 0xf00fffff, 0x00000400,

	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@@ -409,6 +410,7 @@ static const u32 golden_settings_iceland_a11[] = 
	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,

	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,

	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,

	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,

	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,

	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
@@ -505,8 +507,10 @@ static const u32 cz_golden_settings_a11[] = 
	mmGB_GPU_ID, 0x0000000f, 0x00000000,

	mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,

	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,

	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,

	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,

	mmTA_CNTL_AUX, 0x000f000f, 0x00010000,

	mmTCC_CTRL, 0x00100000, 0xf31fff7f,

	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,

	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,

	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+1 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 
		break;

	case CHIP_KAVERI:

	case CHIP_KABINI:

	case CHIP_MULLINS:

		return 0;

	default: BUG();

	}