Merge tag 'phy-for-4.14_v2' of...

mt65xx USB3.0 PHY binding

MediaTek T-PHY binding

--------------------------

This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.

T-phy controller supports physical layer functionality for a number of

controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.

Required properties (controller (parent) node):

 - compatible	: should be one of

		  "mediatek,mt2701-u3phy"

		  "mediatek,mt2712-u3phy"

		  "mediatek,mt8173-u3phy"

		  "mediatek,generic-tphy-v1"

		  "mediatek,generic-tphy-v2"

		  "mediatek,mt2701-u3phy" (deprecated)

		  "mediatek,mt2712-u3phy" (deprecated)

		  "mediatek,mt8173-u3phy";

		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and

		  "mediatek,generic-tphy-v2" on mt2712 instead.

 - clocks	: (deprecated, use port's clocks instead) a list of phandle +

		  clock-specifier pairs, one for each entry in clock-names

 - clock-names	: (deprecated, use port's one instead) must contain

		  cell after port phandle is phy type from:

			- PHY_TYPE_USB2

			- PHY_TYPE_USB3

			- PHY_TYPE_PCIE

			- PHY_TYPE_SATA

Example:

	* "rockchip,rk3328-usb2phy"

	* "rockchip,rk3366-usb2phy"

	* "rockchip,rk3399-usb2phy"

	* "rockchip,rv1108-usb2phy"

 - reg : the address offset of grf for usb-phy configuration.

 - #clock-cells : should be 0.

 - clock-output-names : specify the 480m output clock name.

		 usb-phy output 480m and xin24m.

		 Refer to clk/clock-bindings.txt for generic clock

		 consumer properties.

 - rockchip,usbgrf : phandle to the syscon managing the "usb general

		 register files". When set driver will request its

		 phandle as one companion-grf for some special SoCs

		 (e.g RV1108).

Required nodes : a sub-node is required for each port the phy provides.

		 The sub-node name is used to identify host or otg port,

Required properties (port (child) node):

 - #phy-cells : must be 0. See ./phy-bindings.txt for details.

 - interrupts : specify an interrupt for each entry in interrupt-names.

 - interrupt-names : a list which shall be the following entries:

 - interrupt-names : a list which should be one of the following cases:

	Regular case:

	* "otg-id" : for the otg id interrupt.

	* "otg-bvalid" : for the otg vbus interrupt.

	* "linestate" : for the host/otg linestate interrupt.

	Some SoCs use one interrupt with the above muxed together, so for these

	* "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate

		to one.

Optional properties:

 - phy-supply : phandle to a regulator that provides power to VBUS.

Required properties:

 - compatible: compatible list, contains:

	       "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074

	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,

	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.

		 "phy", "common", "cfg".

		For "qcom,msm8996-qmp-usb3-phy" must contain

		 "phy", "common".

		For "qcom,ipq8074-qmp-pcie-phy" must contain:

		 "phy", "common".

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

	   one for each entry in clock-names.

 - clock-names: Must contain following for pcie and usb qmp phys:

		 "pipe<lane-number>" for pipe clock specific to each lane.

 - clock-output-names: Name of the PHY clock that will be the parent for

		       the above pipe clock.

	For "qcom,ipq8074-qmp-pcie-phy":

		- "pcie20_phy0_pipe_clk"	Pipe Clock parent

			(or)

		  "pcie20_phy1_pipe_clk"

 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

			clock-names = "pipe0";

			clock-output-names = "pcie_0_pipe_clk_src";

			resets = <&gcc GCC_PCIE_0_PHY_BCR>;

			reset-names = "lane0";

		};

Mediatek/Ralink USB PHY

Required properties:

 - compatible: "ralink,rt3352-usbphy"

	       "mediatek,mt7620-usbphy"

	       "mediatek,mt7628-usbphy"

 - reg: required for "mediatek,mt7628-usbphy", unused otherwise

 - #phy-cells: should be 0

 - ralink,sysctl: a phandle to a ralink syscon register region

 - resets: the two reset controllers for host and device

 - reset-names: the names of the 2 reset controllers

Example:

usbphy: phy {

	compatible = "mediatek,mt7628-usbphy";

	reg = <0x10120000 0x1000>;

	#phy-cells = <0>;

	ralink,sysctl = <&sysc>;

	resets = <&rstctrl 22 &rstctrl 25>;

	reset-names = "host", "device";

};

  * allwinner,sun7i-a20-usb-phy

  * allwinner,sun8i-a23-usb-phy

  * allwinner,sun8i-a33-usb-phy

  * allwinner,sun8i-a83t-usb-phy

  * allwinner,sun8i-h3-usb-phy

  * allwinner,sun8i-v3s-usb-phy

  * allwinner,sun50i-a64-usb-phy

  * "phy_ctrl"

  * "pmu0" for H3, V3s and A64

  * "pmu1"

  * "pmu2" for sun4i, sun6i or sun7i

  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "pmu3" for sun8i-h3

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clocks

- clock-names :

  * "usb_phy" for sun4i, sun5i or sun7i

  * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i

  * "usb0_phy", "usb1_phy" for sun8i

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3

- resets : a list of phandle + reset specifier pairs

- reset-names :

  * "usb0_reset"

  * "usb1_reset"

  * "usb2_reset" for sun4i, sun6i or sun7i

  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "usb3_reset" for sun8i-h3

Optional properties:

- usb0_id_det-gpios : gpio phandle for reading the otg id pin value

- usb0_vbus-supply : regulator phandle for controller usb0 vbus

- usb1_vbus-supply : regulator phandle for controller usb1 vbus

- usb2_vbus-supply : regulator phandle for controller usb2 vbus

- usb3_vbus-supply : regulator phandle for controller usb3 vbus

Example:

	usbphy: phy@0x01c13400 {