Merge branches 'at91', 'davinci', 'imx', 'iop', 'ixp', 'ks8695', 'misc', 'pxa' and 's3c' into devel (ca9ced7f) · Commits · e / devices / android_kernel_teracube_emerald

arch/arm/Kconfig

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -241,6 +241,9 @@ config ARCH_H720X

	config ARCH_IMX		config ARCH_IMX
	bool "IMX"		bool "IMX"
			select GENERIC_GPIO
			select GENERIC_TIME
			select GENERIC_CLOCKEVENTS
	help		help
	Support for Motorola's i.MX family of processors (MX1, MXL).		Support for Motorola's i.MX family of processors (MX1, MXL).

	@@ -308,6 +311,7 @@ config ARCH_L7200

	config ARCH_KS8695		config ARCH_KS8695
	bool "Micrel/Kendin KS8695"		bool "Micrel/Kendin KS8695"
			select GENERIC_GPIO
	help		help
	Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based		Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
	System-on-Chip devices.		System-on-Chip devices.
	@@ -384,6 +388,7 @@ config ARCH_DAVINCI
	bool "TI DaVinci"		bool "TI DaVinci"
	select GENERIC_TIME		select GENERIC_TIME
	select GENERIC_CLOCKEVENTS		select GENERIC_CLOCKEVENTS
			select GENERIC_GPIO
	help		help
	Support for TI's DaVinci platform.		Support for TI's DaVinci platform.

arch/arm/boot/compressed/.gitignore

+1 −0

Original line number	Original line	Diff line number	Diff line
	piggy.gz		piggy.gz
			font.c

arch/arm/boot/compressed/Makefile

+7 −6

Original line number	Original line	Diff line number	Diff line
	@@ -6,15 +6,13 @@

	HEAD = head.o		HEAD = head.o
	OBJS = misc.o		OBJS = misc.o
	FONTC = drivers/video/console/font_acorn_8x8.c		FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c

	FONT = $(addprefix ../../../../drivers/video/console/, font_acorn_8x8.o)

	#		#
	# Architecture dependencies		# Architecture dependencies
	#		#
	ifeq ($(CONFIG_ARCH_ACORN),y)		ifeq ($(CONFIG_ARCH_ACORN),y)
	OBJS += ll_char_wr.o $(FONT)		OBJS += ll_char_wr.o font.o
	endif		endif

	ifeq ($(CONFIG_ARCH_SHARK),y)		ifeq ($(CONFIG_ARCH_SHARK),y)
	@@ -73,7 +71,7 @@ endif

	SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/		SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/

	targets := vmlinux vmlinux.lds piggy.gz piggy.o $(FONT) \		targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
	head.o misc.o $(OBJS)		head.o misc.o $(OBJS)
	EXTRA_CFLAGS := -fpic		EXTRA_CFLAGS := -fpic
	EXTRA_AFLAGS :=		EXTRA_AFLAGS :=
	@@ -105,7 +103,10 @@ $(obj)/piggy.gz: $(obj)/../Image FORCE

	$(obj)/piggy.o: $(obj)/piggy.gz FORCE		$(obj)/piggy.o: $(obj)/piggy.gz FORCE

	CFLAGS_font_acorn_8x8.o := -Dstatic=		CFLAGS_font.o := -Dstatic=

			$(obj)/font.c: $(FONTC)
			$(call cmd,shipped)

	$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config		$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config
	@sed "$(SEDFLAGS)" < $< > $@		@sed "$(SEDFLAGS)" < $< > $@

arch/arm/boot/compressed/head-xscale.S

+0 −5

Original line number	Original line	Diff line number	Diff line
	@@ -41,11 +41,6 @@ __XScale_start:
	mov r7, #MACH_TYPE_COTULLA_IDP		mov r7, #MACH_TYPE_COTULLA_IDP
	#endif		#endif

	#ifdef CONFIG_MACH_GTWX5715
	mov r7, #(MACH_TYPE_GTWX5715 & 0xff)
	orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
	#endif

	#ifdef CONFIG_ARCH_IXP2000		#ifdef CONFIG_ARCH_IXP2000
	mov r1, #-1		mov r1, #-1
	mov r0, #0xd6000000		mov r0, #0xd6000000

arch/arm/boot/compressed/head.S

+92 −1

Original line number	Original line	Diff line number	Diff line
	@@ -436,6 +436,28 @@ __armv4_mmu_cache_on:
	mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs		mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
	mov pc, r12		mov pc, r12

			__armv7_mmu_cache_on:
			mov r12, lr
			mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
			tst r11, #0xf @ VMSA
			blne __setup_mmu
			mov r0, #0
			mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
			tst r11, #0xf @ VMSA
			mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
			mrc p15, 0, r0, c1, c0, 0 @ read control reg
			orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
			orr r0, r0, #0x003c @ write buffer
			orrne r0, r0, #1 @ MMU enabled
			movne r1, #-1
			mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
			mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
			mcr p15, 0, r0, c1, c0, 0 @ load control register
			mrc p15, 0, r0, c1, c0, 0 @ and read it back
			mov r0, #0
			mcr p15, 0, r0, c7, c5, 4 @ ISB
			mov pc, r12

	__arm6_mmu_cache_on:		__arm6_mmu_cache_on:
	mov r12, lr		mov r12, lr
	bl __setup_mmu		bl __setup_mmu
	@@ -622,11 +644,17 @@ proc_types:
	b __armv4_mmu_cache_flush		b __armv4_mmu_cache_flush

	.word 0x0007b000 @ ARMv6		.word 0x0007b000 @ ARMv6
	.word 0x0007f000		.word 0x000ff000
	b __armv4_mmu_cache_on		b __armv4_mmu_cache_on
	b __armv4_mmu_cache_off		b __armv4_mmu_cache_off
	b __armv6_mmu_cache_flush		b __armv6_mmu_cache_flush

			.word 0x000f0000 @ new CPU Id
			.word 0x000f0000
			b __armv7_mmu_cache_on
			b __armv7_mmu_cache_off
			b __armv7_mmu_cache_flush

	.word 0 @ unrecognised type		.word 0 @ unrecognised type
	.word 0		.word 0
	mov pc, lr		mov pc, lr
	@@ -674,6 +702,16 @@ __armv4_mmu_cache_off:
	mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4		mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
	mov pc, lr		mov pc, lr

			__armv7_mmu_cache_off:
			mrc p15, 0, r0, c1, c0
			bic r0, r0, #0x000d
			mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
			mov r12, lr
			bl __armv7_mmu_cache_flush
			mov r0, #0
			mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
			mov pc, r12

	__arm6_mmu_cache_off:		__arm6_mmu_cache_off:
	mov r0, #0x00000030 @ ARM6 control reg.		mov r0, #0x00000030 @ ARM6 control reg.
	b __armv3_mmu_cache_off		b __armv3_mmu_cache_off
	@@ -730,6 +768,59 @@ __armv6_mmu_cache_flush:
	mcr p15, 0, r1, c7, c10, 4 @ drain WB		mcr p15, 0, r1, c7, c10, 4 @ drain WB
	mov pc, lr		mov pc, lr

			__armv7_mmu_cache_flush:
			mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
			tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
			beq hierarchical
			mov r10, #0
			mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
			b iflush
			hierarchical:
			stmfd sp!, {r0-r5, r7, r9-r11}
			mrc p15, 1, r0, c0, c0, 1 @ read clidr
			ands r3, r0, #0x7000000 @ extract loc from clidr
			mov r3, r3, lsr #23 @ left align loc bit field
			beq finished @ if loc is 0, then no need to clean
			mov r10, #0 @ start clean at cache level 0
			loop1:
			add r2, r10, r10, lsr #1 @ work out 3x current cache level
			mov r1, r0, lsr r2 @ extract cache type bits from clidr
			and r1, r1, #7 @ mask of the bits for current cache only
			cmp r1, #2 @ see what cache we have at this level
			blt skip @ skip if no cache, or just i-cache
			mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
			mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
			mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
			and r2, r1, #7 @ extract the length of the cache lines
			add r2, r2, #4 @ add 4 (line length offset)
			ldr r4, =0x3ff
			ands r4, r4, r1, lsr #3 @ find maximum number on the way size
			.word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment
			ldr r7, =0x7fff
			ands r7, r7, r1, lsr #13 @ extract max number of the index size
			loop2:
			mov r9, r4 @ create working copy of max way size
			loop3:
			orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
			orr r11, r11, r7, lsl r2 @ factor index number into r11
			mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
			subs r9, r9, #1 @ decrement the way
			bge loop3
			subs r7, r7, #1 @ decrement the index
			bge loop2
			skip:
			add r10, r10, #2 @ increment cache number
			cmp r3, r10
			bgt loop1
			finished:
			mov r10, #0 @ swith back to cache level 0
			mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
			ldmfd sp!, {r0-r5, r7, r9-r11}
			iflush:
			mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
			mcr p15, 0, r10, c7, c10, 4 @ drain WB
			mov pc, lr

	__armv4_mmu_cache_flush:		__armv4_mmu_cache_flush:
	mov r2, #641024 @ default: 32K dcache size (2)		mov r2, #641024 @ default: 32K dcache size (2)
	mov r11, #32 @ default: 32 byte line size		mov r11, #32 @ default: 32 byte line size