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Commit ca320ac4 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Use pixel size for computing linear offsets into a sprite 



This fixes an original bug in the sprite code that miscomputed the
source offset into a linear YUV packed framebuffer, that was magnified
into an oops with

commit 5a35e99e
Author: Damien Lespiau <damien.lespiau@intel.com>
Date:   Fri Oct 26 18:20:12 2012 +0100

    drm/i915: adjust sprite base address

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c16ed4be

drivers/gpu/drm/i915/intel_sprite.c

+4 −6
Original line number Diff line number Diff line
@@ -120,11 +120,10 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	linear_offset = y * fb->pitches[0] + x * pixel_size;

	sprsurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

						 fb->bits_per_pixel / 8,

						 fb->pitches[0]);

						 pixel_size, fb->pitches[0]);

	linear_offset -= sprsurf_offset;



	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
@@ -286,11 +285,10 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	linear_offset = y * fb->pitches[0] + x * pixel_size;

	dvssurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

						 fb->bits_per_pixel / 8,

						 fb->pitches[0]);

						 pixel_size, fb->pitches[0]);

	linear_offset -= dvssurf_offset;



	if (obj->tiling_mode != I915_TILING_NONE)