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Commit ca2942cc authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dt2-for-v4.6' of... 

Merge tag 'renesas-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Second Round of Renesas ARM Based SoC DT Updates for v4.6" from
Simon Horman:

* Add L2 cache-controller nodes to r8a779[0134] and r8a73a4
* Add etheravb support to r8a7794
* Correct JP3 jumper description on Porter
* Enable thermal zone on  r8a779[013]
* Replace gpio-key, wakeup with wakeup-source property on r8a7794
* Use demuxer for IIC0/I2C0 on lager
* Use fallback etheravb, pci and pcie compatibility strings as appropriate

* tag 'renesas-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7790: use fallback etheravb compatibility string
  ARM: dts: r8a7790: lager: use demuxer for IIC0/I2C0
  ARM: dts: r8a7794: add EtherAVB support
  ARM: dts: r8a7794: add EtherAVB clock
  ARM: dts: r8a7794: replace gpio-key, wakeup with wakeup-source property
  ARM: dts: r8a7794: Add L2 cache-controller node
  ARM: dts: r8a7793: Add L2 cache-controller node
  ARM: dts: r8a7791: Add L2 cache-controller node
  ARM: dts: r8a7790: Add L2 cache-controller nodes
  ARM: dts: r8a73a4: Add L2 cache-controller nodes
  ARM: dts: r8a7793: enable to use thermal-zone
  ARM: dts: r8a7791: enable to use thermal-zone
  ARM: dts: r8a7790: enable to use thermal-zone
  ARM: dts: porter: fix JP3 jumper description
  ARM: dts: r8a7794: use fallback pci compatibility string
  ARM: dts: r8a7791: use fallback pci compatibility string
  ARM: dts: r8a7790: use fallback pci compatibility string
  ARM: dts: r8a7791: use fallback pcie compatibility string
  ARM: dts: r8a7790: use fallback pcie compatibility string
parents 7aec2fd7 d92df7e5

arch/arm/boot/dts/r8a73a4.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
			reg = <0>;

			clock-frequency = <1500000000>;

			power-domains = <&pd_a2sl>;

			next-level-cache = <&L2_CA15>;

		};

	};
@@ -45,6 +46,22 @@ 
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	L2_CA15: cache-controller@0 {

		compatible = "cache";

		clocks = <&cpg_clocks R8A73A4_CLK_Z>;

		power-domains = <&pd_a3sm>;

		cache-unified;

		cache-level = <2>;

	};



	L2_CA7: cache-controller@1 {

		compatible = "cache";

		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;

		power-domains = <&pd_a3km>;

		cache-unified;

		cache-level = <2>;

	};



	dbsc1: memory-controller@e6790000 {

		compatible = "renesas,dbsc-r8a73a4";

		reg = <0 0xe6790000 0 0x10000>;

arch/arm/boot/dts/r8a7790-lager.dts

+30 −2
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 * Copyright (C) 2013-2014 Renesas Solutions Corp.

 * Copyright (C) 2014 Cogent Embedded, Inc.

 * Copyright (C) 2015-2016 Renesas Electronics Corporation

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -49,6 +50,7 @@ 
	aliases {

		serial0 = &scif0;

		serial1 = &scifa1;

		i2c8 = "i2cexio";

	};



	chosen {
@@ -252,6 +254,23 @@ 
		#clock-cells = <0>;

		clock-frequency = <148500000>;

	};



	/*

	 * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.

	 * We use the I2C demuxer, so the desired IP core can be selected at runtime

	 * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).

	 * Note: For testing the I2C slave feature, it is convenient to connect this

	 * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and

	 * instantiate the slave device at runtime according to the documentation.

	 * You can then communicate with the slave via IIC3.

	 */

	i2cexio: i2c@8 {

		compatible = "i2c-demux-pinctrl";

		i2c-parent = <&iic0>, <&i2c0>;

		i2c-bus-name = "i2c-exio";

		#address-cells = <1>;

		#size-cells = <0>;

	};

};



&du {
@@ -350,6 +369,11 @@ 
		renesas,function = "msiof1";

	};



	i2c0_pins: i2c0 {

		renesas,groups = "i2c0";

		renesas,function = "i2c0";

	};



	iic0_pins: iic0 {

		renesas,groups = "iic0";

		renesas,function = "iic0";
@@ -537,10 +561,14 @@ 
	cpu0-supply = <&vdd_dvfs>;

};



&i2c0	{

	pinctrl-0 = <&i2c0_pins>;

	pinctrl-names = "i2c-exio";

};



&iic0	{

	status = "okay";

	pinctrl-0 = <&iic0_pins>;

	pinctrl-names = "default";

	pinctrl-names = "i2c-exio";

};



&iic1	{

arch/arm/boot/dts/r8a7790.dtsi

+50 −7
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
			voltage-tolerance = <1>; /* 1% */

			clocks = <&cpg_clocks R8A7790_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */

			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <1>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu2: cpu@2 {
@@ -74,6 +76,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <2>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu3: cpu@3 {
@@ -81,6 +84,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <3>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu4: cpu@4 {
@@ -88,6 +92,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x100>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu5: cpu@5 {
@@ -95,6 +100,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x101>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu6: cpu@6 {
@@ -102,6 +108,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x102>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu7: cpu@7 {
@@ -109,9 +116,41 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x103>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};

	};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive	= <0>;

			polling-delay		= <0>;



			thermal-sensors = <&thermal>;



			trips {

				cpu-crit {

					temperature	= <115000>;

					hysteresis	= <0>;

					type		= "critical";

				};

			};

			cooling-maps {

			};

		};

	};



	L2_CA15: cache-controller@0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

	};



	L2_CA7: cache-controller@1 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

	};



	gic: interrupt-controller@f1001000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;
@@ -202,12 +241,15 @@ 
		power-domains = <&cpg_clocks>;

	};



	thermal@e61f0000 {

		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";

	thermal: thermal@e61f0000 {

		compatible =	"renesas,thermal-r8a7790",

				"renesas,rcar-gen2-thermal",

				"renesas,rcar-thermal";

		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;

		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;

		power-domains = <&cpg_clocks>;

		#thermal-sensor-cells = <0>;

	};



	timer {
@@ -731,7 +773,8 @@ 
	};



	avb: ethernet@e6800000 {

		compatible = "renesas,etheravb-r8a7790";

		compatible = "renesas,etheravb-r8a7790",

			     "renesas,etheravb-rcar-gen2";

		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
@@ -1499,7 +1542,7 @@ 
	};



	pci0: pci@ee090000 {

		compatible = "renesas,pci-r8a7790";

		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";

		device_type = "pci";

		reg = <0 0xee090000 0 0xc00>,

		      <0 0xee080000 0 0x1100>;
@@ -1534,7 +1577,7 @@ 
	};



	pci1: pci@ee0b0000 {

		compatible = "renesas,pci-r8a7790";

		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";

		device_type = "pci";

		reg = <0 0xee0b0000 0 0xc00>,

		      <0 0xee0a0000 0 0x1100>;
@@ -1555,7 +1598,7 @@ 
	};



	pci2: pci@ee0d0000 {

		compatible = "renesas,pci-r8a7790";

		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";

		device_type = "pci";

		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;

		power-domains = <&cpg_clocks>;
@@ -1590,7 +1633,7 @@ 
	};



	pciec: pcie@fe000000 {

		compatible = "renesas,pcie-r8a7790";

		compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";

		reg = <0 0xfe000000 0 0x80000>;

		#address-cells = <3>;

		#size-cells = <2>;

arch/arm/boot/dts/r8a7791-porter.dts

+2 −2
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ 
/*

 * SSI-AK4642

 *

 * SW3: 1: AK4642

 *      3: ADV7511

 * JP3: 2-1: AK4642

 *      2-3: ADV7511

 *

 * This command is required before playback/capture:

 *

arch/arm/boot/dts/r8a7791.dtsi

+35 −5
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
			voltage-tolerance = <1>; /* 1% */

			clocks = <&cpg_clocks R8A7791_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */

			operating-points = <1500000 1000000>,
@@ -66,9 +67,35 @@ 
			compatible = "arm,cortex-a15";

			reg = <1>;

			clock-frequency = <1500000000>;

			next-level-cache = <&L2_CA15>;

		};

	};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive	= <0>;

			polling-delay		= <0>;



			thermal-sensors = <&thermal>;



			trips {

				cpu-crit {

					temperature	= <115000>;

					hysteresis	= <0>;

					type		= "critical";

				};

			};

			cooling-maps {

			};

		};

	};



	L2_CA15: cache-controller@0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

	};



	gic: interrupt-controller@f1001000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;
@@ -185,12 +212,15 @@ 
		power-domains = <&cpg_clocks>;

	};



	thermal@e61f0000 {

		compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";

	thermal: thermal@e61f0000 {

		compatible =	"renesas,thermal-r8a7791",

				"renesas,rcar-gen2-thermal",

				"renesas,rcar-thermal";

		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;

		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;

		power-domains = <&cpg_clocks>;

		#thermal-sensor-cells = <0>;

	};



	timer {
@@ -1530,7 +1560,7 @@ 
	};



	pci0: pci@ee090000 {

		compatible = "renesas,pci-r8a7791";

		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";

		device_type = "pci";

		reg = <0 0xee090000 0 0xc00>,

		      <0 0xee080000 0 0x1100>;
@@ -1565,7 +1595,7 @@ 
	};



	pci1: pci@ee0d0000 {

		compatible = "renesas,pci-r8a7791";

		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";

		device_type = "pci";

		reg = <0 0xee0d0000 0 0xc00>,

		      <0 0xee0c0000 0 0x1100>;
@@ -1600,7 +1630,7 @@ 
	};



	pciec: pcie@fe000000 {

		compatible = "renesas,pcie-r8a7791";

		compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";

		reg = <0 0xfe000000 0 0x80000>;

		#address-cells = <3>;

		#size-cells = <2>;