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Commit c9a3c58f authored by Jintack Lim's avatar Jintack Lim Committed by Marc Zyngier
Browse files

KVM: arm64: Add the EL1 physical timer access handler 



KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.

Signed-off-by: default avatarJintack Lim <jintack@cs.columbia.edu>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent f242adaf

arch/arm64/kvm/sys_regs.c

+34 −0
Original line number Original line Diff line number Diff line
@@ -820,6 +820,30 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\

	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\

	  access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }

	  access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }





static bool access_cntp_tval(struct kvm_vcpu *vcpu,

		struct sys_reg_params *p,

		const struct sys_reg_desc *r)

{

	kvm_inject_undefined(vcpu);

	return true;

}



static bool access_cntp_ctl(struct kvm_vcpu *vcpu,

		struct sys_reg_params *p,

		const struct sys_reg_desc *r)

{

	kvm_inject_undefined(vcpu);

	return true;

}



static bool access_cntp_cval(struct kvm_vcpu *vcpu,

		struct sys_reg_params *p,

		const struct sys_reg_desc *r)

{

	kvm_inject_undefined(vcpu);

	return true;

}



/*

/*

 * Architected system registers.

 * Architected system registers.

 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2

 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -1029,6 +1053,16 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),

	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),

	  NULL, reset_unknown, TPIDRRO_EL0 },

	  NULL, reset_unknown, TPIDRRO_EL0 },





	/* CNTP_TVAL_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),

	  access_cntp_tval },

	/* CNTP_CTL_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),

	  access_cntp_ctl },

	/* CNTP_CVAL_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),

	  access_cntp_cval },



	/* PMEVCNTRn_EL0 */

	/* PMEVCNTRn_EL0 */

	PMU_PMEVCNTR_EL0(0),

	PMU_PMEVCNTR_EL0(0),

	PMU_PMEVCNTR_EL0(1),

	PMU_PMEVCNTR_EL0(1),