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Commit c99d7832 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cfl: Adding more Coffee Lake PCI IDs. 



Spec has been updated with more reserved IDs for existent SKUs.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAnusha <Srivatsa&lt;anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171220182919.21108-1-rodrigo.vivi@intel.com
parent 16a87394

drivers/gpu/drm/i915/i915_pci.c

+2 −0
Original line number Diff line number Diff line
@@ -633,6 +633,8 @@ static const struct pci_device_id pciidlist[] = { 
	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),

	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),

	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),

	INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),

	INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),

include/drm/i915_pciids.h

+22 −6
Original line number Diff line number Diff line
@@ -373,29 +373,45 @@ 
/* CFL S */

#define INTEL_CFL_S_GT1_IDS(info) \

	INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \

	INTEL_VGA_DEVICE(0x3E93, info)  /* SRV GT1 */

	INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \

	INTEL_VGA_DEVICE(0x3E99, info)  /* SRV GT1 */



#define INTEL_CFL_S_GT2_IDS(info) \

	INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \

	INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \

	INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */

	INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \

	INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */



/* CFL H */

#define INTEL_CFL_H_GT2_IDS(info) \

	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \

	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */



/* CFL U */

/* CFL U GT1 */

#define INTEL_CFL_U_GT1_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA1, info), \

	INTEL_VGA_DEVICE(0x3EA4, info)



/* CFL U GT2 */

#define INTEL_CFL_U_GT2_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA0, info), \

	INTEL_VGA_DEVICE(0x3EA3, info), \

	INTEL_VGA_DEVICE(0x3EA9, info)



/* CFL U GT3 */

#define INTEL_CFL_U_GT3_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA5, info)  /* ULT GT3 */

	INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */



#define INTEL_CFL_IDS(info)	   \

	INTEL_CFL_S_GT1_IDS(info), \

	INTEL_CFL_S_GT2_IDS(info), \

	INTEL_CFL_H_GT2_IDS(info), \

	INTEL_CFL_U_GT1_IDS(info), \

	INTEL_CFL_U_GT2_IDS(info), \

	INTEL_CFL_U_GT3_IDS(info)



/* CNL U 2+2 */