Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c93fc287 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  MIPS: csrc-r4k: Fix declaration depending on the wrong CONFIG_ symbol.
  MIPS: csrc-r4k: Fix spelling mistake.
  MIPS: RB532: Provide functions for gpio configuration
  MIPS: IP22: Make indy_sc_ops variable static
  MIPS: RB532: GPIO register offsets are relative to GPIOBASE
  MIPS: Malta: Fix include paths in malta-amon.c
parents e3b4ae79 a24e849c
Loading
Loading
Loading
Loading
+2 −0
Original line number Original line Diff line number Diff line
@@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned
extern unsigned get_434_reg(unsigned reg_offs);
extern unsigned get_434_reg(unsigned reg_offs);
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
extern unsigned char get_latch_u5(void);
extern unsigned char get_latch_u5(void);
extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
extern void rb532_gpio_set_istat(int bit, unsigned gpio);


#endif /* _RC32434_GPIO_H_ */
#endif /* _RC32434_GPIO_H_ */
+8 −6
Original line number Original line Diff line number Diff line
@@ -40,12 +40,14 @@
#define BTCS		0x010040
#define BTCS		0x010040
#define BTCOMPARE	0x010044
#define BTCOMPARE	0x010044
#define GPIOBASE	0x050000
#define GPIOBASE	0x050000
#define GPIOCFG		0x050004
/* Offsets relative to GPIOBASE */
#define GPIOD		0x050008
#define GPIOFUNC	0x00
#define GPIOILEVEL	0x05000C
#define GPIOCFG		0x04
#define GPIOISTAT	0x050010
#define GPIOD		0x08
#define GPIONMIEN	0x050014
#define GPIOILEVEL	0x0C
#define IMASK6		0x038038
#define GPIOISTAT	0x10
#define GPIONMIEN	0x14
#define IMASK6		0x38
#define LO_WPX		(1 << 0)
#define LO_WPX		(1 << 0)
#define LO_ALE		(1 << 1)
#define LO_ALE		(1 << 1)
#define LO_CLE		(1 << 2)
#define LO_CLE		(1 << 2)
+1 −1
Original line number Original line Diff line number Diff line
@@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void)
/*
/*
 * Initialize the count register as a clocksource
 * Initialize the count register as a clocksource
 */
 */
#ifdef CONFIG_CEVT_R4K
#ifdef CONFIG_CSRC_R4K
extern int init_mips_clocksource(void);
extern int init_mips_clocksource(void);
#else
#else
static inline int init_mips_clocksource(void)
static inline int init_mips_clocksource(void)
+1 −1
Original line number Original line Diff line number Diff line
@@ -27,7 +27,7 @@ int __init init_mips_clocksource(void)
	if (!cpu_has_counter || !mips_hpt_frequency)
	if (!cpu_has_counter || !mips_hpt_frequency)
		return -ENXIO;
		return -ENXIO;


	/* Calclate a somewhat reasonable rating value */
	/* Calculate a somewhat reasonable rating value */
	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;


	clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
	clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+1 −1
Original line number Original line Diff line number Diff line
@@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void)


/* XXX Check with wje if the Indy caches can differenciate between
/* XXX Check with wje if the Indy caches can differenciate between
   writeback + invalidate and just invalidate.  */
   writeback + invalidate and just invalidate.  */
struct bcache_ops indy_sc_ops = {
static struct bcache_ops indy_sc_ops = {
	.bc_enable = indy_sc_enable,
	.bc_enable = indy_sc_enable,
	.bc_disable = indy_sc_disable,
	.bc_disable = indy_sc_disable,
	.bc_wback_inv = indy_sc_wback_invalidate,
	.bc_wback_inv = indy_sc_wback_invalidate,
Loading