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Commit c92e8727 authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

drm/omap: HDMI: Fix HSW value 



On OMAP4 and OMAP5 ES1.0 the HDMI_WP_VIDEO_TIMING_H:HSW field is
set directly to the HSW value. On later SoCs the field needs to be
programmed with the value of HSW-1.

Currently the driver always programs the field with the HSW value. Most
videomodes seem to work fine with that, but at least low resolution
interlaced modes don't work at all.

This patch fixes the HSW for OMAP5 ES2.0+ SoCs.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 67d8ffdd

drivers/gpu/drm/omapdrm/dss/hdmi_wp.c

+13 −1
Original line number Original line Diff line number Diff line
@@ -165,12 +165,24 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 
{

{

	u32 timing_h = 0;

	u32 timing_h = 0;

	u32 timing_v = 0;

	u32 timing_v = 0;

	unsigned hsw_offset = 1;





	DSSDBG("Enter hdmi_wp_video_config_timing\n");

	DSSDBG("Enter hdmi_wp_video_config_timing\n");





	/*

	 * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5

	 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1.

	 * However, we don't support OMAP5 ES1 at all, so we can just check for

	 * OMAP4 here.

	 */

	if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||

	    omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||

	    omapdss_get_version() == OMAPDSS_VER_OMAP4)

		hsw_offset = 0;



	timing_h |= FLD_VAL(timings->hbp, 31, 20);

	timing_h |= FLD_VAL(timings->hbp, 31, 20);

	timing_h |= FLD_VAL(timings->hfp, 19, 8);

	timing_h |= FLD_VAL(timings->hfp, 19, 8);

	timing_h |= FLD_VAL(timings->hsw, 7, 0);

	timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0);

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);





	timing_v |= FLD_VAL(timings->vbp, 31, 20);

	timing_v |= FLD_VAL(timings->vbp, 31, 20);