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Commit c8a4364c authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Thomas Gleixner
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x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems 



The McaIntrCfg register (MSRC000_0410), previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20171120162646.5210-1-Yazen.Ghannam@amd.com
parent e085ac7a

arch/x86/kernel/cpu/mcheck/mce_amd.c

+3 −1
Original line number Diff line number Diff line
@@ -407,7 +407,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 
	    (deferred_error_int_vector != amd_deferred_error_interrupt))

		deferred_error_int_vector = amd_deferred_error_interrupt;



	if (!mce_flags.smca)

		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;



	wrmsr(MSR_CU_DEF_ERR, low, high);

}