MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms (c87e0909) · Commits · e / devices / android_kernel_teracube_emerald

arch/mips/Kconfig

+1 −11

Original line number	Original line	Diff line number	Diff line
	@@ -77,7 +77,6 @@ config MIPS_COBALT
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL		select SYS_SUPPORTS_64BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN		select SYS_SUPPORTS_LITTLE_ENDIAN
	select GENERIC_HARDIRQS_NO__DO_IRQ

	config MACH_DECSTATION		config MACH_DECSTATION
	bool "DECstations"		bool "DECstations"
	@@ -132,7 +131,6 @@ config MACH_JAZZ
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL		select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
	select SYS_SUPPORTS_100HZ		select SYS_SUPPORTS_100HZ
	select GENERIC_HARDIRQS_NO__DO_IRQ
	help		help
	This a family of machines based on the MIPS R4030 chipset which was		This a family of machines based on the MIPS R4030 chipset which was
	used by several vendors to build RISC/os and Windows NT workstations.		used by several vendors to build RISC/os and Windows NT workstations.
	@@ -154,7 +152,6 @@ config LASAT
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL if BROKEN		select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
	select SYS_SUPPORTS_LITTLE_ENDIAN		select SYS_SUPPORTS_LITTLE_ENDIAN
	select GENERIC_HARDIRQS_NO__DO_IRQ

	config LEMOTE_FULONG		config LEMOTE_FULONG
	bool "Lemote Fulong mini-PC"		bool "Lemote Fulong mini-PC"
	@@ -175,7 +172,6 @@ config LEMOTE_FULONG
	select SYS_SUPPORTS_LITTLE_ENDIAN		select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_HIGHMEM		select SYS_SUPPORTS_HIGHMEM
	select SYS_HAS_EARLY_PRINTK		select SYS_HAS_EARLY_PRINTK
	select GENERIC_HARDIRQS_NO__DO_IRQ
	select GENERIC_ISA_DMA_SUPPORT_BROKEN		select GENERIC_ISA_DMA_SUPPORT_BROKEN
	select CPU_HAS_WB		select CPU_HAS_WB
	help		help
	@@ -250,7 +246,6 @@ config MACH_VR41XX
	select CEVT_R4K		select CEVT_R4K
	select CSRC_R4K		select CSRC_R4K
	select SYS_HAS_CPU_VR41XX		select SYS_HAS_CPU_VR41XX
	select GENERIC_HARDIRQS_NO__DO_IRQ

	config NXP_STB220		config NXP_STB220
	bool "NXP STB220 board"		bool "NXP STB220 board"
	@@ -364,7 +359,6 @@ config SGI_IP27
	select SYS_SUPPORTS_BIG_ENDIAN		select SYS_SUPPORTS_BIG_ENDIAN
	select SYS_SUPPORTS_NUMA		select SYS_SUPPORTS_NUMA
	select SYS_SUPPORTS_SMP		select SYS_SUPPORTS_SMP
	select GENERIC_HARDIRQS_NO__DO_IRQ
	help		help
	This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics		This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
	workstations. To compile a Linux kernel that runs on these, say Y		workstations. To compile a Linux kernel that runs on these, say Y
	@@ -563,7 +557,6 @@ config MIKROTIK_RB532
	select CEVT_R4K		select CEVT_R4K
	select CSRC_R4K		select CSRC_R4K
	select DMA_NONCOHERENT		select DMA_NONCOHERENT
	select GENERIC_HARDIRQS_NO__DO_IRQ
	select HW_HAS_PCI		select HW_HAS_PCI
	select IRQ_CPU		select IRQ_CPU
	select SYS_HAS_CPU_MIPS32_R1		select SYS_HAS_CPU_MIPS32_R1
	@@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
	default y		default y

	config GENERIC_HARDIRQS_NO__DO_IRQ		config GENERIC_HARDIRQS_NO__DO_IRQ
	bool		def_bool y
	default n

	#		#
	# Select some configuration options automatically based on user selections.		# Select some configuration options automatically based on user selections.
	@@ -920,7 +912,6 @@ config SOC_PNX833X
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_LITTLE_ENDIAN		select SYS_SUPPORTS_LITTLE_ENDIAN
	select SYS_SUPPORTS_BIG_ENDIAN		select SYS_SUPPORTS_BIG_ENDIAN
	select GENERIC_HARDIRQS_NO__DO_IRQ
	select GENERIC_GPIO		select GENERIC_GPIO
	select CPU_MIPSR2_IRQ_VI		select CPU_MIPSR2_IRQ_VI

	@@ -939,7 +930,6 @@ config SOC_PNX8550
	select SYS_HAS_CPU_MIPS32_R1		select SYS_HAS_CPU_MIPS32_R1
	select SYS_HAS_EARLY_PRINTK		select SYS_HAS_EARLY_PRINTK
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select GENERIC_HARDIRQS_NO__DO_IRQ
	select GENERIC_GPIO		select GENERIC_GPIO

	config SWAP_IO_SPACE		config SWAP_IO_SPACE

arch/mips/alchemy/Kconfig

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -134,5 +134,4 @@ config SOC_AU1X00
	select SYS_HAS_CPU_MIPS32_R1		select SYS_HAS_CPU_MIPS32_R1
	select SYS_SUPPORTS_32BIT_KERNEL		select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_APM_EMULATION		select SYS_SUPPORTS_APM_EMULATION
	select GENERIC_HARDIRQS_NO__DO_IRQ
	select ARCH_REQUIRE_GPIOLIB		select ARCH_REQUIRE_GPIOLIB

arch/mips/kernel/irq-msc01.c

+4 −2

Original line number	Original line	Diff line number	Diff line
	@@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma

	switch (imp->im_type) {		switch (imp->im_type) {
	case MSC01_IRQ_EDGE:		case MSC01_IRQ_EDGE:
	set_irq_chip(irqbase+n, &msc_edgeirq_type);		set_irq_chip_and_handler_name(irqbase + n,
			&msc_edgeirq_type, handle_edge_irq, "edge");
	if (cpu_has_veic)		if (cpu_has_veic)
	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);		MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
	else		else
	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT \| imp->im_lvl);		MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT \| imp->im_lvl);
	break;		break;
	case MSC01_IRQ_LEVEL:		case MSC01_IRQ_LEVEL:
	set_irq_chip(irqbase+n, &msc_levelirq_type);		set_irq_chip_and_handler_name(irqbase+n,
			&msc_levelirq_type, handle_level_irq, "level");
	if (cpu_has_veic)		if (cpu_has_veic)
	MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);		MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
	else		else

arch/mips/kernel/irq_cpu.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
	*/		*/
	if (cpu_has_mipsmt)		if (cpu_has_mipsmt)
	for (i = irq_base; i < irq_base + 2; i++)		for (i = irq_base; i < irq_base + 2; i++)
	set_irq_chip(i, &mips_mt_cpu_irq_controller);		set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
			handle_percpu_irq);

	for (i = irq_base + 2; i < irq_base + 8; i++)		for (i = irq_base + 2; i < irq_base + 8; i++)
	set_irq_chip_and_handler(i, &mips_cpu_irq_controller,		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,

arch/mips/sgi-ip32/ip32-irq.c

+45 −18

Original line number	Original line	Diff line number	Diff line
	@@ -325,16 +325,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
	{		{
	unsigned long mace_int;		unsigned long mace_int;

	switch (irq) {
	case MACEISA_PARALLEL_IRQ:
	case MACEISA_SERIAL1_TDMAPR_IRQ:
	case MACEISA_SERIAL2_TDMAPR_IRQ:
	/* edge triggered */		/* edge triggered */
	mace_int = mace->perif.ctrl.istat;		mace_int = mace->perif.ctrl.istat;
	mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));		mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
	mace->perif.ctrl.istat = mace_int;		mace->perif.ctrl.istat = mace_int;
	break;
	}
	disable_maceisa_irq(irq);		disable_maceisa_irq(irq);
	}		}

	@@ -344,7 +339,16 @@ static void end_maceisa_irq(unsigned irq)
	enable_maceisa_irq(irq);		enable_maceisa_irq(irq);
	}		}

	static struct irq_chip ip32_maceisa_interrupt = {		static struct irq_chip ip32_maceisa_level_interrupt = {
			.name = "IP32 MACE ISA",
			.ack = disable_maceisa_irq,
			.mask = disable_maceisa_irq,
			.mask_ack = disable_maceisa_irq,
			.unmask = enable_maceisa_irq,
			.end = end_maceisa_irq,
			};

			static struct irq_chip ip32_maceisa_edge_interrupt = {
	.name = "IP32 MACE ISA",		.name = "IP32 MACE ISA",
	.ack = mask_and_ack_maceisa_irq,		.ack = mask_and_ack_maceisa_irq,
	.mask = disable_maceisa_irq,		.mask = disable_maceisa_irq,
	@@ -500,27 +504,50 @@ void __init arch_init_irq(void)
	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {		for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
	switch (irq) {		switch (irq) {
	case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
	set_irq_chip(irq, &ip32_mace_interrupt);		set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
			handle_level_irq, "level");
	break;		break;

	case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:		case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
	set_irq_chip(irq, &ip32_macepci_interrupt);		set_irq_chip_and_handler_name(irq,
			&ip32_macepci_interrupt, handle_level_irq,
			"level");
	break;		break;

	case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
	set_irq_chip(irq, &crime_edge_interrupt);		set_irq_chip_and_handler_name(irq,
			&crime_edge_interrupt, handle_edge_irq, "edge");
	break;		break;
	case CRIME_CPUERR_IRQ:		case CRIME_CPUERR_IRQ:
	case CRIME_MEMERR_IRQ:		case CRIME_MEMERR_IRQ:
	set_irq_chip(irq, &crime_level_interrupt);		set_irq_chip_and_handler_name(irq,
			&crime_level_interrupt, handle_level_irq,
			"level");
	break;		break;

	case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
	case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
	set_irq_chip(irq, &crime_edge_interrupt);		set_irq_chip_and_handler_name(irq,
			&crime_edge_interrupt, handle_edge_irq, "edge");
	break;		break;

	case CRIME_VICE_IRQ:		case CRIME_VICE_IRQ:
	set_irq_chip(irq, &crime_edge_interrupt);		set_irq_chip_and_handler_name(irq,
			&crime_edge_interrupt, handle_edge_irq, "edge");
	break;		break;

			case MACEISA_PARALLEL_IRQ:
			case MACEISA_SERIAL1_TDMAPR_IRQ:
			case MACEISA_SERIAL2_TDMAPR_IRQ:
			set_irq_chip_and_handler_name(irq,
			&ip32_maceisa_edge_interrupt, handle_edge_irq,
			"edge");
			break;

	default:		default:
	set_irq_chip(irq, &ip32_maceisa_interrupt);		set_irq_chip_and_handler_name(irq,
			&ip32_maceisa_level_interrupt, handle_level_irq,
			"level");
	break;		break;
	}		}
	}		}