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Commit c84b2705 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Extract intel_get_cagf 



Code to be shared between debugfs and the PMU implementation.

v2: Checkpatch cleanup.
v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show.
v4: Rebase.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-1-tvrtko.ursulin@linux.intel.com
parent f9eb63b9

drivers/gpu/drm/i915/i915_debugfs.c

+2 −7
Original line number Diff line number Diff line
@@ -1151,13 +1151,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;

		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;

		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;

		if (INTEL_GEN(dev_priv) >= 9)

			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;

		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;

		else

			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;

		cagf = intel_gpu_freq(dev_priv, cagf);

		cagf = intel_gpu_freq(dev_priv,

				      intel_get_cagf(dev_priv, rpstat));



		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -4226,6 +4226,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,

			   const i915_reg_t reg);



u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);



#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)

#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

drivers/gpu/drm/i915/i915_sysfs.c

+3 −8
Original line number Diff line number Diff line
@@ -252,14 +252,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, 
		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);

	} else {

		u32 rpstat = I915_READ(GEN6_RPSTAT1);

		if (INTEL_GEN(dev_priv) >= 9)

			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;

		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;

		else

			ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;

		ret = intel_gpu_freq(dev_priv, ret);

		ret = intel_gpu_freq(dev_priv,

				     intel_get_cagf(dev_priv,

						    I915_READ(GEN6_RPSTAT1)));

	}

	mutex_unlock(&dev_priv->pcu_lock);

drivers/gpu/drm/i915/intel_pm.c

+14 −0
Original line number Diff line number Diff line
@@ -9468,3 +9468,17 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, 
	intel_runtime_pm_put(dev_priv);

	return DIV_ROUND_UP_ULL(time_hw * units, div);

}



u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)

{

	u32 cagf;



	if (INTEL_GEN(dev_priv) >= 9)

		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;

	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;

	else

		cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;



	return  cagf;

}