Commit c836732f authored May 22, 2014 by Ralf Baechle

MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.



R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has
data cache lines that are always 32 bytes so the call is pointless in
r4k_blast_dcache_page_dc64.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 70e4c234

arch/mips/mm/c-r4k.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -105,7 +105,6 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)

		static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
		{
		R4600_HIT_CACHEOP_WAR_IMPL;
		blast_dcache64_page(addr);
		}