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Commit c7d0045b authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: rename rv1108 macphy clock to mac 



This MAC has no internal phy for rv1108 and the whole clock
infrastructure hasn't been used yet, so is safe to fix.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: default avatarDavid Wu <david.wu@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 10054272

drivers/clk/rockchip/clk-rv1108.c

+6 −6
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 
PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };

PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };

PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };

PNAME(mux_sclk_macphy_p)	= { "ext_gmac", "sclk_macphy_pre" };

PNAME(mux_sclk_mac_p)		= { "ext_gmac", "sclk_mac_pre" };

PNAME(mux_i2s0_pre_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };

PNAME(mux_i2s_out_p)		= { "i2s0_pre", "xin12m" };

PNAME(mux_i2s1_p)		= { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
@@ -755,14 +755,14 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 
			RV1108_CLKGATE_CON(5), 4, GFLAGS),

	GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),



	COMPOSITE(SCLK_MACPHY_PRE, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,

	COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,

			RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,

			RV1108_CLKGATE_CON(4), 10, GFLAGS),

	MUX(SCLK_MACPHY, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,

	MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,

			RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),

	GATE(SCLK_MACPHY_RX, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),

	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),

	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),

	GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),

	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),

	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),

	GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),

	GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),

include/dt-bindings/clock/rv1108-cru.h

+3 −3
Original line number Diff line number Diff line
@@ -67,9 +67,9 @@ 
#define SCLK_SPI			108

#define SCLK_SARADC			109

#define SCLK_TSADC			110

#define SCLK_MACPHY_PRE			111

#define SCLK_MACPHY			112

#define SCLK_MACPHY_RX			113

#define SCLK_MAC_PRE			111

#define SCLK_MAC			112

#define SCLK_MAC_RX			113

#define SCLK_MAC_REF			114

#define SCLK_MAC_REFOUT			115

#define SCLK_DSP_PFM			116