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Commit c47f8684 authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
Browse files

ARM: perf: remove active_mask 



Currently, pmu_hw_events::active_mask is used to keep track of which
events are active in hardware. As we can stop counters and their
interrupts, this is unnecessary.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Reviewed-by: default avatarJamie Iles <jamie@jamieiles.com>
Reviewed-by: default avatarAshwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 7b9f72c6

arch/arm/kernel/perf_event.c

+0 −8
Original line number Diff line number Diff line
@@ -57,12 +57,6 @@ struct cpu_hw_events { 
	 * an event. A 0 means that the counter can be used.

	 */

	unsigned long		used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];



	/*

	 * A 1 bit for an index indicates that the counter is actively being

	 * used.

	 */

	unsigned long		active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];

};

static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
@@ -295,7 +289,6 @@ armpmu_del(struct perf_event *event, int flags) 


	WARN_ON(idx < 0);



	clear_bit(idx, cpuc->active_mask);

	armpmu_stop(event, PERF_EF_UPDATE);

	cpuc->events[idx] = NULL;

	clear_bit(idx, cpuc->used_mask);
@@ -327,7 +320,6 @@ armpmu_add(struct perf_event *event, int flags) 
	event->hw.idx = idx;

	armpmu->disable(hwc, idx);

	cpuc->events[idx] = event;

	set_bit(idx, cpuc->active_mask);



	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;

	if (flags & PERF_EF_START)

arch/arm/kernel/perf_event_v6.c

+18 −1
Original line number Diff line number Diff line
@@ -462,6 +462,23 @@ armv6pmu_enable_event(struct hw_perf_event *hwc, 
	raw_spin_unlock_irqrestore(&pmu_lock, flags);

}



static int counter_is_active(unsigned long pmcr, int idx)

{

	unsigned long mask = 0;

	if (idx == ARMV6_CYCLE_COUNTER)

		mask = ARMV6_PMCR_CCOUNT_IEN;

	else if (idx == ARMV6_COUNTER0)

		mask = ARMV6_PMCR_COUNT0_IEN;

	else if (idx == ARMV6_COUNTER1)

		mask = ARMV6_PMCR_COUNT1_IEN;



	if (mask)

		return pmcr & mask;



	WARN_ONCE(1, "invalid counter number (%d)\n", idx);

	return 0;

}



static irqreturn_t

armv6pmu_handle_irq(int irq_num,

		    void *dev)
@@ -491,7 +508,7 @@ armv6pmu_handle_irq(int irq_num, 
		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;



		if (!test_bit(idx, cpuc->active_mask))

		if (!counter_is_active(pmcr, idx))

			continue;



		/*

arch/arm/kernel/perf_event_v7.c

+0 −3
Original line number Diff line number Diff line
@@ -1022,9 +1022,6 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) 
		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;



		if (!test_bit(idx, cpuc->active_mask))

			continue;



		/*

		 * We have a single interrupt for all counters. Check that

		 * each counter has overflowed before we process it.

arch/arm/kernel/perf_event_xscale.c

+0 −6
Original line number Diff line number Diff line
@@ -253,9 +253,6 @@ xscale1pmu_handle_irq(int irq_num, void *dev) 
		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;



		if (!test_bit(idx, cpuc->active_mask))

			continue;



		if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))

			continue;
@@ -585,9 +582,6 @@ xscale2pmu_handle_irq(int irq_num, void *dev) 
		struct perf_event *event = cpuc->events[idx];

		struct hw_perf_event *hwc;



		if (!test_bit(idx, cpuc->active_mask))

			continue;



		if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))

			continue;