Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c2a560f5 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Add some missing board headers. 



Some of these were dropped in the header directory rework, add
the few missing ones back in.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 1f666587

include/asm-sh/edosk7705.h

0 → 100644
+30 −0
Original line number Original line Diff line number Diff line 
/*

 * include/asm-sh/edosk7705/io.h

 *

 * Modified version of io_se.h for the EDOSK7705 specific functions.

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 *

 * IO functions for an Hitachi EDOSK7705 development board

 */



#ifndef __ASM_SH_EDOSK7705_IO_H

#define __ASM_SH_EDOSK7705_IO_H



#include <asm/io_generic.h>



extern unsigned char sh_edosk7705_inb(unsigned long port);

extern unsigned int sh_edosk7705_inl(unsigned long port);



extern void sh_edosk7705_outb(unsigned char value, unsigned long port);

extern void sh_edosk7705_outl(unsigned int value, unsigned long port);



extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);

extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);

extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);

extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);



extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);



#endif /* __ASM_SH_EDOSK7705_IO_H */

include/asm-sh/hp6xx.h

0 → 100644
+80 −0
Original line number Original line Diff line number Diff line 
#ifndef __ASM_SH_HP6XX_H

#define __ASM_SH_HP6XX_H



/*

 * Copyright (C) 2003, 2004, 2005  Andriy Skulysh

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 */



#define HP680_BTN_IRQ		IRQ0_IRQ

#define HP680_TS_IRQ		IRQ3_IRQ

#define HP680_HD64461_IRQ	IRQ4_IRQ



#define DAC_LCD_BRIGHTNESS	0

#define DAC_SPEAKER_VOLUME	1



#define PGDR_OPENED		0x01

#define PGDR_MAIN_BATTERY_OUT	0x04

#define PGDR_PLAY_BUTTON	0x08

#define PGDR_REWIND_BUTTON	0x10

#define PGDR_RECORD_BUTTON	0x20



#define PHDR_TS_PEN_DOWN	0x08



#define PJDR_LED_BLINK		0x02



#define PKDR_LED_GREEN		0x10



#define SCPDR_TS_SCAN_ENABLE	0x20

#define SCPDR_TS_SCAN_Y		0x02

#define SCPDR_TS_SCAN_X		0x01



#define SCPCR_TS_ENABLE		0x405

#define SCPCR_TS_MASK		0xc0f



#define ADC_CHANNEL_TS_Y	1

#define ADC_CHANNEL_TS_X	2

#define ADC_CHANNEL_BATTERY	3

#define ADC_CHANNEL_BACKUP	4

#define ADC_CHANNEL_CHARGE	5



#define HD64461_GPADR_SPEAKER	0x01

#define HD64461_GPADR_PCMCIA0	(0x02|0x08)



#define HD64461_GPBDR_LCDOFF	0x01

#define HD64461_GPBDR_LCD_CONTRAST_MASK	0x78

#define HD64461_GPBDR_LED_RED	0x80



#include <asm/hd64461.h>

#include <asm/io.h>



#define PJDR	0xa4000130

#define PKDR	0xa4000132



static inline void hp6xx_led_red(int on)

{

	u16 v16;

	v16 = ctrl_inw(CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);

	if (on)

	    ctrl_outw(v16 & (~HD64461_GPBDR_LED_RED), CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);

	else

	    ctrl_outw(v16 | HD64461_GPBDR_LED_RED, CONFIG_HD64461_IOBASE + HD64461_GPBDR - 0x10000);

}



static inline void hp6xx_led_green(int on)

{

	u8 v8;



	v8 = ctrl_inb(PKDR);

	if (on)

	    ctrl_outb(v8 & (~PKDR_LED_GREEN), PKDR);

	else

	    ctrl_outb(v8 | PKDR_LED_GREEN, PKDR);

}





#endif /* __ASM_SH_HP6XX_H */

include/asm-sh/hs7751rvoip.h

0 → 100644
+54 −0
Original line number Original line Diff line number Diff line 
#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H

#define __ASM_SH_RENESAS_HS7751RVOIP_H



/*

 * linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h

 *

 * Copyright (C) 2000  Atom Create Engineering Co., Ltd.

 *

 * Renesas Technology Sales HS7751RVoIP support

 */



/* Box specific addresses.  */



#define PA_BCR		0xa4000000	/* FPGA */

#define PA_SLICCNTR1	0xa4000006	/* SLIC PIO Control 1 */

#define PA_SLICCNTR2	0xa4000008	/* SLIC PIO Control 2 */

#define PA_DMACNTR	0xa400000a	/* USB DMA Control */

#define PA_INPORTR	0xa400000c	/* Input Port Register */

#define PA_OUTPORTR	0xa400000e	/* Output Port Reguster */

#define PA_VERREG	0xa4000014	/* FPGA Version Register */



#define PA_IDE_OFFSET	0x1f0		/* CF IDE Offset */



#define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */

#define IRLCNTR2	(PA_BCR + 2)	/* Interrupt Control Register2 */

#define IRLCNTR3	(PA_BCR + 4)	/* Interrupt Control Register3 */

#define IRLCNTR4	(PA_BCR + 16)	/* Interrupt Control Register4 */

#define IRLCNTR5	(PA_BCR + 18)	/* Interrupt Control Register5 */



#define IRQ_PCIETH	6		/* PCI Ethernet IRQ */

#define IRQ_PCIHUB	7		/* PCI Ethernet Hub IRQ */

#define IRQ_USBCOM	8		/* USB Comunication IRQ */

#define IRQ_USBCON	9		/* USB Connect IRQ */

#define IRQ_USBDMA	10		/* USB DMA IRQ */

#define IRQ_CFCARD	11		/* CF Card IRQ */

#define IRQ_PCMCIA	12		/* PCMCIA IRQ */

#define IRQ_PCISLOT	13		/* PCI Slot #1 IRQ */

#define IRQ_ONHOOK1	0		/* ON HOOK1 IRQ */

#define IRQ_OFFHOOK1	1		/* OFF HOOK1 IRQ */

#define IRQ_ONHOOK2	2		/* ON HOOK2 IRQ */

#define IRQ_OFFHOOK2	3		/* OFF HOOK2 IRQ */

#define	IRQ_RINGING	4		/* Ringing IRQ */

#define	IRQ_CODEC	5		/* CODEC IRQ */



#define __IO_PREFIX	hs7751rvoip

#include <asm/io_generic.h>



/* arch/sh/boards/renesas/hs7751rvoip/irq.c */

void init_hs7751rvoip_IRQ(void);



/* arch/sh/boards/renesas/hs7751rvoip/io.c */

void *hs7751rvoip_ioremap(unsigned long, unsigned long);



#endif  /* __ASM_SH_RENESAS_HS7751RVOIP */

include/asm-sh/r7780rp.h

0 → 100644
+173 −0
Original line number Original line Diff line number Diff line 
#ifndef __ASM_SH_RENESAS_R7780RP_H

#define __ASM_SH_RENESAS_R7780RP_H



/*

 * linux/include/asm-sh/r7780rp.h

 *

 * Copyright (C) 2000  Atom Create Engineering Co., Ltd.

 *

 * Renesas Solutions Highlander R7780RP support

 */



/* Box specific addresses.  */

#if defined(CONFIG_SH_R7780MP)

#define PA_BCR          0xa4000000      /* FPGA */

#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */

#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */

#define PA_IRLPRI1      (PA_BCR+0x0004) /* Interrupt Priorty 1 */

#define PA_IRLPRI2      (PA_BCR+0x0006) /* Interrupt Priorty 2 */

#define PA_IRLPRI3      (PA_BCR+0x0008) /* Interrupt Priorty 3 */

#define PA_IRLPRI4      (PA_BCR+0x000a) /* Interrupt Priorty 4 */

#define PA_RSTCTL       (PA_BCR+0x000c) /* Reset Control */

#define PA_PCIBD        (PA_BCR+0x000e) /* PCI Board detect control */

#define PA_PCICD        (PA_BCR+0x0010) /* PCI Conector detect control */

#define PA_EXTGIO       (PA_BCR+0x0016) /* Extension GPIO Control */

#define PA_IVDRMON      (PA_BCR+0x0018) /* iVDR Moniter control */

#define PA_IVDRCTL      (PA_BCR+0x001a) /* iVDR control */

#define PA_OBLED        (PA_BCR+0x001c) /* On Board LED control */

#define PA_OBSW         (PA_BCR+0x001e) /* On Board Switch control */

#define PA_AUDIOSEL     (PA_BCR+0x0020) /* Sound Interface Select control */

#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */

#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */

#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */

#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */

#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */

#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */

#define PA_DBSW         (PA_BCR+0x0200) /* Debug Board Switch control */

#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */

#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */

#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */

#define PA_SCSMR0       (PA_BCR+0x0400) /* SCIF0 Serial mode control */

#define PA_SCBRR0       (PA_BCR+0x0404) /* SCIF0 Bit rate control */

#define PA_SCSCR0       (PA_BCR+0x0408) /* SCIF0 Serial control */

#define PA_SCFTDR0      (PA_BCR+0x040c) /* SCIF0 Send FIFO control */

#define PA_SCFSR0       (PA_BCR+0x0410) /* SCIF0 Serial status control */

#define PA_SCFRDR0      (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */

#define PA_SCFCR0       (PA_BCR+0x0418) /* SCIF0 FIFO control */

#define PA_SCTFDR0      (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */

#define PA_SCRFDR0      (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */

#define PA_SCSPTR0      (PA_BCR+0x0424) /* SCIF0 Serial Port control */

#define PA_SCLSR0       (PA_BCR+0x0428) /* SCIF0 Line Status control */

#define PA_SCRER0       (PA_BCR+0x042c) /* SCIF0 Serial Error control */

#define PA_SCSMR1       (PA_BCR+0x0500) /* SCIF1 Serial mode control */

#define PA_SCBRR1       (PA_BCR+0x0504) /* SCIF1 Bit rate control */

#define PA_SCSCR1       (PA_BCR+0x0508) /* SCIF1 Serial control */

#define PA_SCFTDR1      (PA_BCR+0x050c) /* SCIF1 Send FIFO control */

#define PA_SCFSR1       (PA_BCR+0x0510) /* SCIF1 Serial status control */

#define PA_SCFRDR1      (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */

#define PA_SCFCR1       (PA_BCR+0x0518) /* SCIF1 FIFO control */

#define PA_SCTFDR1      (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */

#define PA_SCRFDR1      (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */

#define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */

#define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */

#define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */

#define PA_ICCR         (PA_BCR+0x0600) /* Serial control */

#define PA_SAR          (PA_BCR+0x0602) /* Serial Slave control */

#define PA_MDR          (PA_BCR+0x0604) /* Serial Mode control */

#define PA_ADR1         (PA_BCR+0x0606) /* Serial Address1 control */

#define PA_DAR1         (PA_BCR+0x0646) /* Serial Data1 control */

#define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */

#define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */

#define PA_PMR          (PA_BCR+0x0900) /*  */



#define PA_AX88796L     0xa4100400      /* AX88796L Area */

#define PA_SC1602BSLB   0xa6000000      /* SC1602BSLB Area */

#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */

#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */



#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */



#define IRQ_PCISLOT1    65              /* PCI Slot #1 IRQ */

#define IRQ_PCISLOT2    66              /* PCI Slot #2 IRQ */

#define IRQ_PCISLOT3    67              /* PCI Slot #3 IRQ */

#define IRQ_PCISLOT4    68              /* PCI Slot #4 IRQ */

#define IRQ_CFCARD      1               /* CF Card IRQ */

// #define IRQ_CFINST   0               /* CF Card Insert IRQ */

#define IRQ_TP          2               /* Touch Panel IRQ */

#define IRQ_SCI1        3               /* SCI1 IRQ */

#define IRQ_SCI0        4               /* SCI0 IRQ */

#define IRQ_2SERIAL     5               /* Serial IRQ */

#define IRQ_RTC         6               /* RTC A / B IRQ */

#define IRQ_EXTENTION6  7               /* EXT6n IRQ */

#define IRQ_EXTENTION5  8               /* EXT5n IRQ */

#define IRQ_EXTENTION4  9               /* EXT4n IRQ */

#define IRQ_EXTENTION2  10              /* EXT2n IRQ */

#define IRQ_EXTENTION1  11              /* EXT1n IRQ */

#define IRQ_ONETH       13              /* On board Ethernet IRQ */

#define IRQ_PSW         14              /* Push Switch IRQ */



#else /* R7780RP */



#define PA_BCR		0xa5000000	/* FPGA */

#define	PA_IRLMSK	(PA_BCR+0x0000)	/* Interrupt Mask control */

#define PA_IRLMON	(PA_BCR+0x0002)	/* Interrupt Status control */

#define	PA_SDPOW	(PA_BCR+0x0004)	/* SD Power control */

#define	PA_RSTCTL	(PA_BCR+0x0006)	/* Device Reset control */

#define	PA_PCIBD	(PA_BCR+0x0008)	/* PCI Board detect control */

#define	PA_PCICD	(PA_BCR+0x000a)	/* PCI Conector detect control */

#define	PA_ZIGIO1	(PA_BCR+0x000c)	/* Zigbee IO control 1 */

#define	PA_ZIGIO2	(PA_BCR+0x000e)	/* Zigbee IO control 2 */

#define	PA_ZIGIO3	(PA_BCR+0x0010)	/* Zigbee IO control 3 */

#define	PA_ZIGIO4	(PA_BCR+0x0012)	/* Zigbee IO control 4 */

#define	PA_IVDRMON	(PA_BCR+0x0014)	/* iVDR Moniter control */

#define	PA_IVDRCTL	(PA_BCR+0x0016)	/* iVDR control */

#define PA_OBLED	(PA_BCR+0x0018)	/* On Board LED control */

#define PA_OBSW		(PA_BCR+0x001a)	/* On Board Switch control */

#define PA_AUDIOSEL	(PA_BCR+0x001c)	/* Sound Interface Select control */

#define PA_EXTPLR	(PA_BCR+0x001e)	/* Extention Pin Polarity control */

#define PA_TPCTL	(PA_BCR+0x0100)	/* Touch Panel Access control */

#define PA_TPDCKCTL	(PA_BCR+0x0102)	/* Touch Panel Access data control */

#define PA_TPCTLCLR	(PA_BCR+0x0104)	/* Touch Panel Access control */

#define PA_TPXPOS	(PA_BCR+0x0106)	/* Touch Panel X position control */

#define PA_TPYPOS	(PA_BCR+0x0108)	/* Touch Panel Y position control */

#define PA_DBDET	(PA_BCR+0x0200)	/* Debug Board detect control */

#define PA_DBDISPCTL	(PA_BCR+0x0202)	/* Debug Board Dot timing control */

#define PA_DBSW		(PA_BCR+0x0204)	/* Debug Board Switch control */

#define PA_CFCTL	(PA_BCR+0x0300)	/* CF Timing control */

#define PA_CFPOW	(PA_BCR+0x0302)	/* CF Power control */

#define PA_CFCDINTCLR	(PA_BCR+0x0304)	/* CF Insert Interrupt clear */

#define PA_SCSMR	(PA_BCR+0x0400)	/* SCIF Serial mode control */

#define PA_SCBRR	(PA_BCR+0x0402)	/* SCIF Bit rate control */

#define PA_SCSCR	(PA_BCR+0x0404)	/* SCIF Serial control */

#define PA_SCFDTR	(PA_BCR+0x0406)	/* SCIF Send FIFO control */

#define PA_SCFSR	(PA_BCR+0x0408)	/* SCIF Serial status control */

#define PA_SCFRDR	(PA_BCR+0x040a)	/* SCIF Receive FIFO control */

#define PA_SCFCR	(PA_BCR+0x040c)	/* SCIF FIFO control */

#define PA_SCFDR	(PA_BCR+0x040e)	/* SCIF FIFO data control */

#define PA_SCLSR	(PA_BCR+0x0412)	/* SCIF Line Status control */

#define PA_ICCR		(PA_BCR+0x0500)	/* Serial control */

#define PA_SAR		(PA_BCR+0x0502)	/* Serial Slave control */

#define PA_MDR		(PA_BCR+0x0504)	/* Serial Mode control */

#define PA_ADR1		(PA_BCR+0x0506)	/* Serial Address1 control */

#define PA_DAR1		(PA_BCR+0x0546)	/* Serial Data1 control */

#define PA_VERREG	(PA_BCR+0x0600)	/* FPGA Version Register */



#define PA_AX88796L	0xa5800400	/* AX88796L Area */

#define PA_SC1602BSLB	0xa6000000	/* SC1602BSLB Area */

#define PA_IDE_OFFSET	0x1f0		/* CF IDE Offset */

#define AX88796L_IO_BASE	0x1000	/* AX88796L IO Base Address */



#define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */



#define IRQ_PCISLOT1	0		/* PCI Slot #1 IRQ */

#define IRQ_PCISLOT2	1		/* PCI Slot #2 IRQ */

#define IRQ_PCISLOT3	2		/* PCI Slot #3 IRQ */

#define IRQ_PCISLOT4	3		/* PCI Slot #4 IRQ */

#define IRQ_CFCARD	4		/* CF Card IRQ */

#define IRQ_CFINST	5		/* CF Card Insert IRQ */

#define IRQ_M66596	6		/* M66596 IRQ */

#define IRQ_SDCARD	7		/* SD Card IRQ */

#define IRQ_TUCHPANEL	8		/* Touch Panel IRQ */

#define IRQ_SCI		9		/* SCI IRQ */

#define IRQ_2SERIAL	10		/* Serial IRQ */

#define	IRQ_EXTENTION	11		/* EXTn IRQ */

#define IRQ_ONETH	12		/* On board Ethernet IRQ */

#define IRQ_PSW		13		/* Push Switch IRQ */

#define IRQ_ZIGBEE	14		/* Ziggbee IO IRQ */



#endif  /* CONFIG_SH_R7780MP */



#define __IO_PREFIX	r7780rp

#include <asm/io_generic.h>



#endif  /* __ASM_SH_RENESAS_R7780RP */

include/asm-sh/rts7751r2d.h

0 → 100644
+74 −0
Original line number Original line Diff line number Diff line 
#ifndef __ASM_SH_RENESAS_RTS7751R2D_H

#define __ASM_SH_RENESAS_RTS7751R2D_H



/*

 * linux/include/asm-sh/renesas_rts7751r2d.h

 *

 * Copyright (C) 2000  Atom Create Engineering Co., Ltd.

 *

 * Renesas Technology Sales RTS7751R2D support

 */



/* Box specific addresses.  */



#define PA_BCR		0xa4000000	/* FPGA */

#define PA_IRLMON	0xa4000002	/* Interrupt Status control */

#define PA_CFCTL	0xa4000004	/* CF Timing control */

#define PA_CFPOW	0xa4000006	/* CF Power control */

#define PA_DISPCTL	0xa4000008	/* Display Timing control */

#define PA_SDMPOW	0xa400000a	/* SD Power control */

#define PA_RTCCE	0xa400000c	/* RTC(9701) Enable control */

#define PA_PCICD	0xa400000e	/* PCI Extention detect control */

#define PA_VOYAGERRTS	0xa4000020	/* VOYAGER Reset control */

#if defined(CONFIG_RTS7751R2D_REV11)

#define PA_AXRST	0xa4000022	/* AX_LAN Reset control */

#define PA_CFRST	0xa4000024	/* CF Reset control */

#define	PA_ADMRTS	0xa4000026	/* SD Reset control */

#define PA_EXTRST	0xa4000028	/* Extention Reset control */

#define PA_CFCDINTCLR	0xa400002a	/* CF Insert Interrupt clear */

#else

#define PA_CFRST	0xa4000022	/* CF Reset control */

#define	PA_ADMRTS	0xa4000024	/* SD Reset control */

#define PA_EXTRST	0xa4000026	/* Extention Reset control */

#define PA_CFCDINTCLR	0xa4000028	/* CF Insert Interrupt clear */

#define	PA_KEYCTLCLR	0xa400002a	/* Key Interrupt clear */

#endif

#define PA_POWOFF	0xa4000030	/* Board Power OFF control */

#define PA_VERREG	0xa4000032	/* FPGA Version Register */

#define PA_INPORT	0xa4000034	/* KEY Input Port control */

#define PA_OUTPORT	0xa4000036	/* LED control */

#define PA_DMPORT	0xa4000038	/* DM270 Output Port control */



#define PA_AX88796L	0xaa000400	/* AX88796L Area */

#define PA_VOYAGER	0xab000000	/* VOYAGER GX Area */

#define PA_IDE_OFFSET	0x1f0		/* CF IDE Offset */

#define AX88796L_IO_BASE	0x1000	/* AX88796L IO Base Address */



#define IRLCNTR1	(PA_BCR + 0)	/* Interrupt Control Register1 */



#if defined(CONFIG_RTS7751R2D_REV11)

#define IRQ_PCIETH	0		/* PCI Ethernet IRQ */

#define IRQ_CFCARD	1		/* CF Card IRQ */

#define IRQ_CFINST	2		/* CF Card Insert IRQ */

#define IRQ_PCMCIA	3		/* PCMCIA IRQ */

#define IRQ_VOYAGER	4		/* VOYAGER IRQ */

#define IRQ_ONETH	5		/* On board Ethernet IRQ */

#else

#define IRQ_KEYIN	0		/* Key Input IRQ */

#define IRQ_PCIETH	1		/* PCI Ethernet IRQ */

#define IRQ_CFCARD	2		/* CF Card IRQ */

#define IRQ_CFINST	3		/* CF Card Insert IRQ */

#define IRQ_PCMCIA	4		/* PCMCIA IRQ */

#define IRQ_VOYAGER	5		/* VOYAGER IRQ */

#endif

#define IRQ_RTCALM	6		/* RTC Alarm IRQ */

#define IRQ_RTCTIME	7		/* RTC Timer IRQ */

#define IRQ_SDCARD	8		/* SD Card IRQ */

#define IRQ_PCISLOT1	9		/* PCI Slot #1 IRQ */

#define IRQ_PCISLOT2	10		/* PCI Slot #2 IRQ */

#define	IRQ_EXTENTION	11		/* EXTn IRQ */



#define __IO_PREFIX rts7751r2d

#include <asm/io_generic.h>



#endif  /* __ASM_SH_RENESAS_RTS7751R2D */