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Unverified Commit c235edcb authored by Giulio Benetti's avatar Giulio Benetti Committed by Maxime Ripard
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ARM: dts: sun8i-h3: Add Mali node 



The H3 has an ARM Mali 400 GPU, so add binding to our DT.

Signed-off-by: default avatarGiulio Benetti <giulio.benetti@micronovasrl.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 22821975

Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required properties: 
    * And, optionally, one of the vendor specific compatible:

      + allwinner,sun4i-a10-mali

      + allwinner,sun7i-a20-mali

      + allwinner,sun8i-h3-mali

      + allwinner,sun50i-h5-mali

      + amlogic,meson-gxbb-mali

      + amlogic,meson-gxl-mali

arch/arm/boot/dts/sun8i-h3.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -79,6 +79,33 @@ 
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	soc {

		mali: gpu@1c40000 {

			compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";

			reg = <0x01c40000 0x10000>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp",

					  "gpmmu",

					  "pp0",

					  "ppmmu0",

					  "pp1",

					  "ppmmu1",

					  "pmu";

			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;

			clock-names = "bus", "core";

			resets = <&ccu RST_BUS_GPU>;



			assigned-clocks = <&ccu CLK_GPU>;

			assigned-clock-rates = <384000000>;

		};

	};

};



&ccu {