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Commit c1e81a3b authored by James Liao's avatar James Liao Committed by Stephen Boyd
Browse files

clk: mediatek: Add basic clocks for Mediatek MT8173. 



This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
INFRA and PERI clocks.

Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: default avatarHenry Chen <henryc.chen@mediatek.com>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent a8aede79

drivers/clk/mediatek/Makefile

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obj-y += clk-mtk.o clk-pll.o clk-gate.o

obj-$(CONFIG_RESET_CONTROLLER) += reset.o

obj-y += clk-mt8135.o

obj-y += clk-mt8173.o

drivers/clk/mediatek/clk-mt8173.c

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File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/mt8173-clk.h

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/*

 * Copyright (c) 2014 MediaTek Inc.

 * Author: James Liao <jamesjj.liao@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MT8173_H

#define _DT_BINDINGS_CLK_MT8173_H



/* TOPCKGEN */



#define CLK_TOP_CLKPH_MCK_O		1

#define CLK_TOP_DPI			2

#define CLK_TOP_USB_SYSPLL_125M		3

#define CLK_TOP_HDMITX_DIG_CTS		4

#define CLK_TOP_ARMCA7PLL_754M		5

#define CLK_TOP_ARMCA7PLL_502M		6

#define CLK_TOP_MAIN_H546M		7

#define CLK_TOP_MAIN_H364M		8

#define CLK_TOP_MAIN_H218P4M		9

#define CLK_TOP_MAIN_H156M		10

#define CLK_TOP_TVDPLL_445P5M		11

#define CLK_TOP_TVDPLL_594M		12

#define CLK_TOP_UNIV_624M		13

#define CLK_TOP_UNIV_416M		14

#define CLK_TOP_UNIV_249P6M		15

#define CLK_TOP_UNIV_178P3M		16

#define CLK_TOP_UNIV_48M		17

#define CLK_TOP_CLKRTC_EXT		18

#define CLK_TOP_CLKRTC_INT		19

#define CLK_TOP_FPC			20

#define CLK_TOP_HDMITXPLL_D2		21

#define CLK_TOP_HDMITXPLL_D3		22

#define CLK_TOP_ARMCA7PLL_D2		23

#define CLK_TOP_ARMCA7PLL_D3		24

#define CLK_TOP_APLL1			25

#define CLK_TOP_APLL2			26

#define CLK_TOP_DMPLL			27

#define CLK_TOP_DMPLL_D2		28

#define CLK_TOP_DMPLL_D4		29

#define CLK_TOP_DMPLL_D8		30

#define CLK_TOP_DMPLL_D16		31

#define CLK_TOP_LVDSPLL_D2		32

#define CLK_TOP_LVDSPLL_D4		33

#define CLK_TOP_LVDSPLL_D8		34

#define CLK_TOP_MMPLL			35

#define CLK_TOP_MMPLL_D2		36

#define CLK_TOP_MSDCPLL			37

#define CLK_TOP_MSDCPLL_D2		38

#define CLK_TOP_MSDCPLL_D4		39

#define CLK_TOP_MSDCPLL2		40

#define CLK_TOP_MSDCPLL2_D2		41

#define CLK_TOP_MSDCPLL2_D4		42

#define CLK_TOP_SYSPLL_D2		43

#define CLK_TOP_SYSPLL1_D2		44

#define CLK_TOP_SYSPLL1_D4		45

#define CLK_TOP_SYSPLL1_D8		46

#define CLK_TOP_SYSPLL1_D16		47

#define CLK_TOP_SYSPLL_D3		48

#define CLK_TOP_SYSPLL2_D2		49

#define CLK_TOP_SYSPLL2_D4		50

#define CLK_TOP_SYSPLL_D5		51

#define CLK_TOP_SYSPLL3_D2		52

#define CLK_TOP_SYSPLL3_D4		53

#define CLK_TOP_SYSPLL_D7		54

#define CLK_TOP_SYSPLL4_D2		55

#define CLK_TOP_SYSPLL4_D4		56

#define CLK_TOP_TVDPLL			57

#define CLK_TOP_TVDPLL_D2		58

#define CLK_TOP_TVDPLL_D4		59

#define CLK_TOP_TVDPLL_D8		60

#define CLK_TOP_TVDPLL_D16		61

#define CLK_TOP_UNIVPLL_D2		62

#define CLK_TOP_UNIVPLL1_D2		63

#define CLK_TOP_UNIVPLL1_D4		64

#define CLK_TOP_UNIVPLL1_D8		65

#define CLK_TOP_UNIVPLL_D3		66

#define CLK_TOP_UNIVPLL2_D2		67

#define CLK_TOP_UNIVPLL2_D4		68

#define CLK_TOP_UNIVPLL2_D8		69

#define CLK_TOP_UNIVPLL_D5		70

#define CLK_TOP_UNIVPLL3_D2		71

#define CLK_TOP_UNIVPLL3_D4		72

#define CLK_TOP_UNIVPLL3_D8		73

#define CLK_TOP_UNIVPLL_D7		74

#define CLK_TOP_UNIVPLL_D26		75

#define CLK_TOP_UNIVPLL_D52		76

#define CLK_TOP_VCODECPLL		77

#define CLK_TOP_VCODECPLL_370P5		78

#define CLK_TOP_VENCPLL			79

#define CLK_TOP_VENCPLL_D2		80

#define CLK_TOP_VENCPLL_D4		81

#define CLK_TOP_AXI_SEL			82

#define CLK_TOP_MEM_SEL			83

#define CLK_TOP_DDRPHYCFG_SEL		84

#define CLK_TOP_MM_SEL			85

#define CLK_TOP_PWM_SEL			86

#define CLK_TOP_VDEC_SEL		87

#define CLK_TOP_VENC_SEL		88

#define CLK_TOP_MFG_SEL			89

#define CLK_TOP_CAMTG_SEL		90

#define CLK_TOP_UART_SEL		91

#define CLK_TOP_SPI_SEL			92

#define CLK_TOP_USB20_SEL		93

#define CLK_TOP_USB30_SEL		94

#define CLK_TOP_MSDC50_0_H_SEL		95

#define CLK_TOP_MSDC50_0_SEL		96

#define CLK_TOP_MSDC30_1_SEL		97

#define CLK_TOP_MSDC30_2_SEL		98

#define CLK_TOP_MSDC30_3_SEL		99

#define CLK_TOP_AUDIO_SEL		100

#define CLK_TOP_AUD_INTBUS_SEL		101

#define CLK_TOP_PMICSPI_SEL		102

#define CLK_TOP_SCP_SEL			103

#define CLK_TOP_ATB_SEL			104

#define CLK_TOP_VENC_LT_SEL		105

#define CLK_TOP_DPI0_SEL		106

#define CLK_TOP_IRDA_SEL		107

#define CLK_TOP_CCI400_SEL		108

#define CLK_TOP_AUD_1_SEL		109

#define CLK_TOP_AUD_2_SEL		110

#define CLK_TOP_MEM_MFG_IN_SEL		111

#define CLK_TOP_AXI_MFG_IN_SEL		112

#define CLK_TOP_SCAM_SEL		113

#define CLK_TOP_SPINFI_IFR_SEL		114

#define CLK_TOP_HDMI_SEL		115

#define CLK_TOP_DPILVDS_SEL		116

#define CLK_TOP_MSDC50_2_H_SEL		117

#define CLK_TOP_HDCP_SEL		118

#define CLK_TOP_HDCP_24M_SEL		119

#define CLK_TOP_RTC_SEL			120

#define CLK_TOP_APLL1_DIV0		121

#define CLK_TOP_APLL1_DIV1		122

#define CLK_TOP_APLL1_DIV2		123

#define CLK_TOP_APLL1_DIV3		124

#define CLK_TOP_APLL1_DIV4		125

#define CLK_TOP_APLL1_DIV5		126

#define CLK_TOP_APLL2_DIV0		127

#define CLK_TOP_APLL2_DIV1		128

#define CLK_TOP_APLL2_DIV2		129

#define CLK_TOP_APLL2_DIV3		130

#define CLK_TOP_APLL2_DIV4		131

#define CLK_TOP_APLL2_DIV5		132

#define CLK_TOP_I2S0_M_SEL		133

#define CLK_TOP_I2S1_M_SEL		134

#define CLK_TOP_I2S2_M_SEL		135

#define CLK_TOP_I2S3_M_SEL		136

#define CLK_TOP_I2S3_B_SEL		137

#define CLK_TOP_NR_CLK			138



/* APMIXED_SYS */



#define CLK_APMIXED_ARMCA15PLL	1

#define CLK_APMIXED_ARMCA7PLL	2

#define CLK_APMIXED_MAINPLL		3

#define CLK_APMIXED_UNIVPLL		4

#define CLK_APMIXED_MMPLL		5

#define CLK_APMIXED_MSDCPLL		6

#define CLK_APMIXED_VENCPLL		7

#define CLK_APMIXED_TVDPLL		8

#define CLK_APMIXED_MPLL		9

#define CLK_APMIXED_VCODECPLL		10

#define CLK_APMIXED_APLL1		11

#define CLK_APMIXED_APLL2		12

#define CLK_APMIXED_LVDSPLL		13

#define CLK_APMIXED_MSDCPLL2		14

#define CLK_APMIXED_NR_CLK		15



/* INFRA_SYS */



#define CLK_INFRA_DBGCLK		1

#define CLK_INFRA_SMI			2

#define CLK_INFRA_AUDIO			3

#define CLK_INFRA_GCE			4

#define CLK_INFRA_L2C_SRAM		5

#define CLK_INFRA_M4U			6

#define CLK_INFRA_CPUM			7

#define CLK_INFRA_KP			8

#define CLK_INFRA_CEC			9

#define CLK_INFRA_PMICSPI		10

#define CLK_INFRA_PMICWRAP		11

#define CLK_INFRA_NR_CLK		12



/* PERI_SYS */



#define CLK_PERI_NFI			1

#define CLK_PERI_THERM			2

#define CLK_PERI_PWM1			3

#define CLK_PERI_PWM2			4

#define CLK_PERI_PWM3			5

#define CLK_PERI_PWM4			6

#define CLK_PERI_PWM5			7

#define CLK_PERI_PWM6			8

#define CLK_PERI_PWM7			9

#define CLK_PERI_PWM			10

#define CLK_PERI_USB0			11

#define CLK_PERI_USB1			12

#define CLK_PERI_AP_DMA			13

#define CLK_PERI_MSDC30_0		14

#define CLK_PERI_MSDC30_1		15

#define CLK_PERI_MSDC30_2		16

#define CLK_PERI_MSDC30_3		17

#define CLK_PERI_NLI_ARB		18

#define CLK_PERI_IRDA			19

#define CLK_PERI_UART0			20

#define CLK_PERI_UART1			21

#define CLK_PERI_UART2			22

#define CLK_PERI_UART3			23

#define CLK_PERI_I2C0			24

#define CLK_PERI_I2C1			25

#define CLK_PERI_I2C2			26

#define CLK_PERI_I2C3			27

#define CLK_PERI_I2C4			28

#define CLK_PERI_AUXADC			29

#define CLK_PERI_SPI0			30

#define CLK_PERI_I2C5			31

#define CLK_PERI_NFIECC			32

#define CLK_PERI_SPI			33

#define CLK_PERI_IRRX			34

#define CLK_PERI_I2C6			35

#define CLK_PERI_UART0_SEL		36

#define CLK_PERI_UART1_SEL		37

#define CLK_PERI_UART2_SEL		38

#define CLK_PERI_UART3_SEL		39

#define CLK_PERI_NR_CLK			40



#endif /* _DT_BINDINGS_CLK_MT8173_H */

include/dt-bindings/reset-controller/mt8173-resets.h

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/*

 * Copyright (c) 2014 MediaTek Inc.

 * Author: Flora Fu, MediaTek

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173

#define _DT_BINDINGS_RESET_CONTROLLER_MT8173



/* INFRACFG resets */

#define MT8173_INFRA_EMI_REG_RST        0

#define MT8173_INFRA_DRAMC0_A0_RST      1

#define MT8173_INFRA_APCIRQ_EINT_RST    3

#define MT8173_INFRA_APXGPT_RST         4

#define MT8173_INFRA_SCPSYS_RST         5

#define MT8173_INFRA_KP_RST             6

#define MT8173_INFRA_PMIC_WRAP_RST      7

#define MT8173_INFRA_MPIP_RST           8

#define MT8173_INFRA_CEC_RST            9

#define MT8173_INFRA_EMI_RST            32

#define MT8173_INFRA_DRAMC0_RST         34

#define MT8173_INFRA_APMIXEDSYS_RST     35

#define MT8173_INFRA_MIPI_DSI_RST       36

#define MT8173_INFRA_TRNG_RST           37

#define MT8173_INFRA_SYSIRQ_RST         38

#define MT8173_INFRA_MIPI_CSI_RST       39

#define MT8173_INFRA_GCE_FAXI_RST       40

#define MT8173_INFRA_MMIOMMURST         47





/*  PERICFG resets */

#define MT8173_PERI_UART0_SW_RST        0

#define MT8173_PERI_UART1_SW_RST        1

#define MT8173_PERI_UART2_SW_RST        2

#define MT8173_PERI_UART3_SW_RST        3

#define MT8173_PERI_IRRX_SW_RST         4

#define MT8173_PERI_PWM_SW_RST          8

#define MT8173_PERI_AUXADC_SW_RST       10

#define MT8173_PERI_DMA_SW_RST          11

#define MT8173_PERI_I2C6_SW_RST         13

#define MT8173_PERI_NFI_SW_RST          14

#define MT8173_PERI_THERM_SW_RST        16

#define MT8173_PERI_MSDC2_SW_RST        17

#define MT8173_PERI_MSDC3_SW_RST        18

#define MT8173_PERI_MSDC0_SW_RST        19

#define MT8173_PERI_MSDC1_SW_RST        20

#define MT8173_PERI_I2C0_SW_RST         22

#define MT8173_PERI_I2C1_SW_RST         23

#define MT8173_PERI_I2C2_SW_RST         24

#define MT8173_PERI_I2C3_SW_RST         25

#define MT8173_PERI_I2C4_SW_RST         26

#define MT8173_PERI_HDMI_SW_RST         29

#define MT8173_PERI_SPI0_SW_RST         33



#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */