Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c1a9ae43 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: De-magic the VLV p2 divider step size 



The p2 divider on VLV needs to be even when it's > 10. The current code
to make that happen is rather weird. Just make the step size adjustement
in the for loop decrement step.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6b4bf1c4

drivers/gpu/drm/i915/intel_display.c

+2 −3
Original line number Diff line number Diff line
@@ -688,9 +688,8 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, 
	/* based on hardware requirement, prefer smaller n to precision */

	for (clock.n = limit->n.min; clock.n <= ((refclk) / minupdate); clock.n++) {

		for (clock.p1 = limit->p1.max; clock.p1 > limit->p1.min; clock.p1--) {

			for (clock.p2 = limit->p2.p2_fast+1; clock.p2 > 0; clock.p2--) {

				if (clock.p2 > 10)

					clock.p2--;

			for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0;

			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {

				clock.p = clock.p1 * clock.p2;

				/* based on hardware requirement, prefer bigger m1,m2 values */

				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {