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Commit c182d2b7 authored by Ashok Raj's avatar Ashok Raj Committed by Thomas Gleixner
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x86/microcode/intel: Check microcode revision before updating sibling threads 



After updating microcode on one of the threads of a core, the other
thread sibling automatically gets the update since the microcode
resources on a hyperthreaded core are shared between the two threads.

Check the microcode revision on the CPU before performing a microcode
update and thus save us the WRMSR 0x79 because it is a particularly
expensive operation.

[ Borislav: Massage changelog and coding style. ]

Signed-off-by: default avatarAshok Raj <ashok.raj@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Tested-by: default avatarAshok Raj <ashok.raj@intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
Link: http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok.raj@intel.com
Link: https://lkml.kernel.org/r/20180228102846.13447-3-bp@alien8.de
parent 854857f5

arch/x86/kernel/cpu/microcode/intel.c

+24 −3
Original line number Diff line number Diff line
@@ -589,6 +589,17 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) 
	if (!mc)

		return 0;



	/*

	 * Save us the MSR write below - which is a particular expensive

	 * operation - when the other hyperthread has updated the microcode

	 * already.

	 */

	rev = intel_get_microcode_revision();

	if (rev >= mc->hdr.rev) {

		uci->cpu_sig.rev = rev;

		return UCODE_OK;

	}



	/* write microcode via MSR 0x79 */

	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_intel(int cpu) 
{

	struct microcode_intel *mc;

	struct ucode_cpu_info *uci;

	struct cpuinfo_x86 *c;

	struct cpuinfo_x86 *c = &cpu_data(cpu);

	static int prev_rev;

	u32 rev;
@@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_intel(int cpu) 
			return UCODE_NFOUND;

	}



	/*

	 * Save us the MSR write below - which is a particular expensive

	 * operation - when the other hyperthread has updated the microcode

	 * already.

	 */

	rev = intel_get_microcode_revision();

	if (rev >= mc->hdr.rev) {

		uci->cpu_sig.rev = rev;

		c->microcode = rev;

		return UCODE_OK;

	}



	/* write microcode via MSR 0x79 */

	wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_intel(int cpu) 
		prev_rev = rev;

	}



	c = &cpu_data(cpu);



	uci->cpu_sig.rev = rev;

	c->microcode = rev;